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| ispXPLD 5000MX Family 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLDTM Family August 2004 Data Sheet TM Features Flexible Multi-Function Block (MFB) Architecture * * * * * SuperWIDETM logic (up to 136 inputs) Arithmetic capability Single- or Dual-port SRAM FIFO Ternary CAM Expanded In-System Programmability (ispXPTM) * Instant-on capability * Single chip convenience * In-System Programmable via IEEE 1532 Interface * Infinitely reconfigurable via IEEE 1532 or sysCONFIGTM microprocessor interface * Design security sysCLOCKTM PLL Timing Control * Multiply and divide between 1 and 32 * Clock shifting capability * External feedback capability High Speed Operation * 4.0ns pin-to-pin delays, 300MHz fMAX * Deterministic timing Low Power Consumption * Typical static power: 20 to 50mA (1.8V), 30 to 60mA (2.5/3.3V) * 1.8V core for low dynamic power sysIOTM Interfaces * LVCMOS 1.8, 2.5, 3.3V - Programmable impedance - Hot-socketing - Flexible bus-maintenance (Pull-up, pulldown, bus-keeper, or none) - Open drain operation * SSTL 2, 3 (I & II) * HSTL (I, III, IV) * PCI 3.3 * GTL+ * LVDS * LVPECL * LVTTL Table 1. ispXPLD 5000MX Family Selection Guide ispXPLD 5256MX Macrocells Multi-Function Blocks Maximum RAM Bits Maximum CAM Bits sysCLOCK PLLs tPD (Propagation Delay) tS (Register Set-up Time) tCO (Register Clock to Out Time) fMAX (Maximum Operating Frequency) System Gates I/Os Packages 256 fpBGA 256 8 128K 48K 2 4.0ns 2.2ns 2.8ns 300MHz 75K 141 Easy System Integration * 3.3V (5000MV), 2.5V (5000MB) and 1.8V (5000MC) power supply operation * 5V tolerant I/O for LVCMOS 3.3 and LVTTL interfaces * IEEE 1149.1 interface for boundary scan testing * sysIO quick configuration * Density migration * Multiple density and package options * PQFP and fine pitch BGA packaging * Lead-free package options ispXPLD 5512MX 512 16 256K 96K 2 4.5ns 2.8ns 3.0ns 275MHz 150K 149/193/253 208 PQFP 256 fpBGA 484 fpBGA ispXPLD 5768MX ispXPLD 51024MX 768 24 384K 144K 2 5.0ns 2.8ns 3.2ns 250MHz 225K 193/317 256 fpBGA 484 fpBGA 1,024 32 512K 192K 2 5.2ns 3.0ns 3.7ns 250MHz 300K 317/381 484 fpBGA 672 fpBGA (c) 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 5kmx_10 Lattice Semiconductor Figure 1. ispXPLD 5000MX Block Diagram PROGRAM ispXPLD 5000MX Family Data Sheet TDO VCCJ GND TMS TCK VCC ISP Port VCCO0 VREF0 sysIO Bank 0 OSA TDI VCCO3 VREF3 MFB MFB sysIO Bank 3 OSA MFB GCLCK0 VCCP GNDP GCLK1 sysIO Bank 1 Optional sysCONFIG Interface MFB GCLCK3 Global Routing Pool (GRP) sysCLOCK PLL 0 sysCLOCK PLL 1 GCLK2 MFB MFB sysIO Bank 2 RESET GOE0 GOE1 VREF2 VCCO2 OSA OSA VREF1 VCCO1 MFB MFB Introduction The ispXPLD 5000MX family represents a new class of device, referred to as the eXpanded Programmable Logic Devices (XPLDs). These devices extend the capability of Lattice's popular SuperWIDE ispMACH 5000 architecture by providing flexible memory capability. The family supports single- or dual-port SRAM, FIFO, and ternary CAM operation. Extra logic has also been included to allow efficient implementation of arithmetic functions. In addition, sysCLOCK PLLs and sysIO interfaces provide support for the system-level needs of designers. The devices provide designers with a convenient one-chip solution that provides logic availability at boot-up, design security, and extreme reconfigurability. The use of advanced process technology provides industry-leading performance with combinatorial propagation delay as low as 4.0ns, 2.8ns clock-to-out delay, 2.2ns set-up time, and operating frequency up to 300MHz. This performance is coupled with low static and dynamic power consumption. The ispXPLD 5000MX architecture provides predictable deterministic timing. The availability of 3.3, 2.5 and 1.8V versions of these devices along with the flexibility of the sysIO interface helps users meet the challenge of today's mixed voltage designs. Inputs can be safely driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. Boundary scan testability further eases integration into today's complex systems. A variety of density and package options increase the likelihood of a good fit for a particular application. Table 1 shows the members of the ispXPLD 5000MX family. Architecture The ispXPLD 5000MX devices consist of Multi-Function Blocks (MFBs) interconnected with a Global Routing Pool. Signals enter and leave the device via one of four sysIO banks. Figure 1 shows the block diagram of the ispXPLD 2 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet 5000MX. Incoming signals may connect to the global routing pool or the registers in the MFBs. An Output Sharing Array (OSA) increases the number of I/O available to each MFB, allowing a complete function high-performance access to the I/O. There are four clock pins that drive four global clock nets within the device. Two sysCLOCK PLLs are provided to allow the synthesis of new clocks and control of clock skews. Multi-Function Block (MFB) Each MFB in the ispXPLD 5000MX architecture can be configured in one of the six following modes. This provides a flexible approach to implementing logic and memory that allows the designer to achieve the mix of functions that are required for a particular design, maximizing resource utilization. The six modes supported by the MFB are: * * * * * * SuperWIDE Logic Mode True Dual-port SRAM Mode Pseudo Dual-port SRAM Mode Single-port SRAM Mode FIFO Mode Ternary CAM Mode The MFB consists of a multi-function array and associated routing. Depending on the chosen functions the multifunction array uses up to 68 inputs from the GRP and the four global clock and reset signals. The array outputs data along with certain control functions to the macrocells. Output signals can be routed internally for use elsewhere in the device and to the sysIO banks for output. Figure 2 shows the block diagram of the MFB. The various configurations are described in more detail in the following sections. Figure 2. MFB Block Diagram Cascade In CLK0 CLK1 CLK2 CLK3 Reset To Routing Multifunction Array True Dual Port RAM (8,192 bit) Single Port RAM (16,384 bit) FIFO (16,384 bit) Ternary CAM (128*48) Logic (68 Input * 164 Product Term Array, 32 MC) PTOE Sharing Cascade Out 3 To I/O via OSA (16,384 bit) 32 Feedback Signals Pseudo Dual Port RAM Lattice Semiconductor Cascading For Wide Operation ispXPLD 5000MX Family Data Sheet In several modes it is possible to cascade adjacent MFBs to support wider operation. Table 2 details the different cascading options. There are chains of MFBs in each device which determine those MFBs that are adjacent for the purposes of cascading. Table 3 indicates these chains. The ispXPLD 5000MX design tools automatically cascade blocks if required by a particular design. Table 2. Cascading Modes For Wide Support Mode Logic FIFO CAM Cascading Function Input Width. Allows two MFBs to act as a 136-input block. Arithmetic. Allow the carry chain to pass between two MFBs. Memory Width Expansion. Allows MFBs to be cascaded for greater width support. Memory Width Expansion. Allows up to four MFBs to be cascaded for greater width support. Table 3. MFB Cascade Chain Device ispXPLD 5256MX ispXPLD 5512MX ispXPLD 5768MX ispXPLD 51024MX ABCD H -> G -> F -> E ABCDEFGH PNMLKJI DCBAXWVUTSRQ EFGHIJKLMNOP H G F E D C B A AF AE AD AC AB AA Z Y IJKLMNOPQRSTUVWX MFBs in Cascade Chain SuperWIDE Logic Mode In logic mode, each MFB contains 32 macrocells and a fully populated, programmable AND-array with 160 logic product terms and four control product terms. The MFB has 68 inputs from the Global Routing Pool, which are available in both true and complement form for every product term. It is also possible to cascade adjacent MFBs to create a block with 136 inputs. The four control product terms are used for shared reset, clock, clock enable, and output enable functions. Figure 3 shows the overall structure of the MFB in logic mode while Figure 4 provides a more detailed view from the perspective of a macrocell slice. 4 Lattice Semiconductor Figure 3. MFB in SuperWIDE Logic Mode CLK0 CLK1 CLK2 CLK3 Reset Carry In ispXPLD 5000MX Family Data Sheet To Routing Dual-OR Gate PT Sharing Array 68 inputs 164 P-Term 32 Macrocells 68 Inputs from Adjacent MFB Shared PT Clk Shared PT Clk En Shared PT Reset PTOE Sharing Carry Out Figure 4. Macrocell Slice in Logic Mode AND-Array From GRP From Carry-in n-7 PT OE to I/O Block From I/O Cell PTSA Bypass Output to I/O Block D PTSA PT Clock Shared PT CE 68 Q Clk En GRP R/L Shared PTCLK CLK0 CLK1 CLK2 CLK3 Clk PR PT Preset PT Reset Shared PT Reset Global Reset AND Array Dual-OR Array To Carry-out n+7 Macrocell 5 To I/O via OSA 68 Inputs from Routing 32 Macrocell Feedback Signals AND Array Lattice Semiconductor AND-Array ispXPLD 5000MX Family Data Sheet The programmable AND-Array consists of 68 inputs and 164 output product terms. The 68 inputs from the GRP are used to form 136 lines in the AND-Array (true and complement of the inputs). Each line in the array can be connected to any of the 164 output product terms via a wired AND. Each of the 160 logic product terms feed the DualOR Array with the remaining four control product terms feeding the Shared PT Clock, Shared PT Clock Enable, Shared PT Reset and Shared PT OE. Starting with PT0 sets of five product terms form product term clusters. There is one product term cluster for every macrocell in the MFB. In addition to the four control product terms, the first, third, fourth and fifth product terms of each cluster can be used as a PTOE, PT Clock, PT Preset and PT Reset, respectively. Figure 5 is a graphical representation of the AND-Array. Figure 5. AND Array In[0] In[66] In[67] PT0 PT1 PT2 PT3 PT4 Cluster 0 PT155 PT156 PT157 Cluster 31 PT158 PT159 PT160 Shared clock enable PT161 Shared clock PT162 Shared reset PT163 Shared OE Note: Indicates programmable fuse. Dual-OR Array (Including Arithmetic Support) The Dual-OR Array consists of 64 OR gates. There are two OR gates per macrocell in the MFB. These OR gates are referred to as the Expandable PTSA OR gate and the PTSA-Bypass OR gate. The PTSA-Bypass OR gate receives its five inputs from the combination of product terms associated with the product term cluster. The PTSABypass OR gate feeds the macrocell directly for fast narrow logic. The Expandable PTSA OR gate receives five inputs from the combination of product terms associated with the product term cluster. It also receives an additional input from the Expanded PTSA OR gate of the N-7 macrocell, where N is the number of the macrocell associated with the current OR gate. The Expandable PTSA OR gate feeds the PTSA for sharing with other product terms and the N+7 Expandable PTSA OR gate. This allows cascading of multiple OR gates for wide functions. There is a small timing adder for each level of expansion. Figure 6 is a graphical representation of the Dual-OR Array. The Dual-OR PT sharing array also contains logic to aid in the efficient implementation of arithmetic functions. This logic takes Carry In and allows the generation of Carry Out along with a SUM signal. Subtractors can be implemented using the two's complement method. Carry is propagated from macrocells 0 to macrocell 31. Macrocell zero can have its carry input connected to the carry output of macrocell 31 in an adjacent MFB or it can be set to zero or one. If a macrocell is not used in an arithmetic function carry can bypass it. The carry chain flows is the same as that for PT cascading. 6 Lattice Semiconductor Figure 6. Dual-OR PT Sharing Array From Carry n-7 In From PT0 ispXPLD 5000MX Family Data Sheet PT OE To I/O Block From PT1 PTSA Bypass To Macrocell From PT2 N To PTSA To Macrocell PT Clock From PT3 PT Preset To Macrocell From PT4 PT Reset To Macrocell To n+7 Carry Out Product Term Sharing Array The Product Term Sharing Array (PTSA) consists of 32 inputs from the Dual-OR Array (Expandable PTSA OR) and 32 outputs directly to the macrocells. Each output is the OR term of any combination of the seven Expandable PTSA OR terms connected to that output. Every Nth macrocell is connected to N-3, N-2, N-1, N, N+1, N+2 and N+3 PTSA OR terms via a programmable connection. This wraps around the logic, for example, Macrocell 0 gets its logic from 29, 30, 31, 0, 1, 2, 3. The Expandable PTSA OR used in conjunction with the PTSA allows wide functions to be implemented easily and efficiently. Without using the Expandable PTSA OR capability, the greatest number of product terms that can be included in a single function with one pass of delay is 35. Up to 160 product terms can be included in a single function through the use of the expandable PTSA OR capability. Figure 7 shows the graphical representation of the PTSA. Figure 7. Product Term Sharing Array (PTSA) PTSA OR 0 PTSA OR 1 PTSA OR 2 PTSA OR 3 Macrocell 0 Macrocell 1 Macrocell 2 PTSA OR 29 PTSA OR 30 PTSA OR 31 Macrocell 29 Macrocell 30 Macrocell 31 7 Lattice Semiconductor Macrocell ispXPLD 5000MX Family Data Sheet The 32 registered macrocells in the MFB are driven by the 32 outputs from the PTSA or the PTSA bypass. Each macrocell contains a programmable XOR gate, a programmable register/latch flip-flop and the necessary clocks and control logic to allow combinatorial or registered operation. All macrocells have an output that feeds the GRP. Selected macrocells have an additional output that feeds the OSA and hence I/Os. This dual or concurrent output capability from the macrocell gives efficient use of the hardware resources. One output can be a registered function for example, while the other output can be an unrelated combinatorial function. A direct register input from the I/O cell facilitates efficient use of the macrocell to construct high-speed input registers. Macrocell registers can be clocked from one of several global or product term clocks available on the device. A global and product term clock enable is also provided, eliminating the need to gate the clock to the macrocell registers directly. Reset and preset for the macrocell register is provided from both global and product term signals. The macrocell register can be programmed to operate as a D-type register or a D-type latch. Figure 8 is a graphical representation of the macrocell. Figure 8. Macrocell From I/O Cell PTSA Bypass Output to I/O Block From PTSA PT Clock Shared PT CE D Q Clk En GRP R/L Shared PT Clock CLK0 CLK1 CLK2 CLK3 Clk P R PT Preset PT Reset Shared PT Reset Global Reset Memory Modes The ispXPLD 5000MX architecture allows the MFB to be configured as a variety of memory blocks as detailed in Table 4. The remainder of this section details operation of each of the memory modes. Additional information regarding the memory modes can also be found in technical note number TN1030, Using Memory in ispXPLD 5000MX Devices. 8 Lattice Semiconductor Table 4. MFB Memory Configuration Memory Mode Dual-port ispXPLD 5000MX Family Data Sheet Max. Configuration Size1 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 8 512 x 16 16,384 x1 8,192 x 2 4,096 x 4 2,048 x 8 1,024 x 16 512 x 32 128 x 48 Single-port, Pseudo Dual Port, FIFO CAM 1. Smaller configurations are possible. Input and Output The data input and control signals to a MFB in memory mode are generated from inputs from the routing. Data signals are only available in the true non-inverted format. True or complemented versions of the inputs are available for generating the control signals. Data and flag outputs are fed from the MFB to the GRP and OSA. Unused inputs and outputs are not accessible in memory mode. ROM Operation In each of the memory modes it is possible to specify the power-on state of each bit in the memory array. This allows the memory to be used as ROM if desired. Increased Depth And Width Designs that require a memory depth or width that is greater than that support by a single MFB can be supported by cascading multiple blocks. For dual port, single port, and pseudo dual port modes additional width is easily provided by sharing address lines. Additional depth is supported by multiplexing the RAM output. For FIFO and CAM modes additional width is supported through the cascading of MFBs. The Lattice design tools automatically combine blocks to support the memory size specified in the user's design. Bus Size Matching All of the memory modes apart from CAM mode support different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for each port varies this mapping scheme applies to each port. 9 Lattice Semiconductor True Dual-Port SRAM Mode ispXPLD 5000MX Family Data Sheet In Dual-Port SRAM Mode the multi-function array is configured as a dual port SRAM. In this mode two independent read/write ports access the same 8,192-bits of memory. Data widths of 1, 2, 4, 8, and 16 are supported by the MFB. Figure 9 shows the block diagram of the dual port SRAM. Write data, address, chip select and read/write signals are always synchronous (registered.) The output data signals can be synchronous or asynchronous. Resets are asynchronous. All inputs on the same port share the same clock, clock enable, and reset selections. All outputs on the same port share the same clock, clock enable, and reset selections. Selections may be made independently between both inputs and outputs and ports. Table 5 shows the possible sources for the clock, clock enable and initialization signals for the various registers. Figure 9. Dual-Port SRAM Block Diagram CLK0 CLK1 CLK2 CLK3 RESET PORT A Read/Write Address (ADA[0:8-12]) RD Data A (DOA[0:0-15]) Reset A (RSTA) Clock A (CLKA) Clk En A (CENA) Write/Read A (WRA) 68 Inputs From Routing Chip Sel A (CSA [0:1]) Write Data (DIA[0:0,1,3,7,15]) ` ` Dual Port SRAM Array PORT B Similar signals as PORT A: ADB[0:8-12], RSTB, CLKB, CENB, WRB, CSB[0,1], DIB[0:0,1,3,7,15] RD Data B (DOB[0:0-15]) Table 5. Register Clock, Clock Enable, and Reset in Dual-Port SRAM Mode Register Address, Write Data, Read Data, Read/ Write, and Chip Select Input Clock Clock Enable Reset Source CLKA (CLKB) or one of the global clocks (CLK0 - CLK3). The selected signal can be inverted if desired. CENA (CENB) or one of the global clocks (CLK1 - CLK 2). The selected signal can be inverted if required. Created by the logical OR of the global reset signal and RSTA (RSTB). RSTA (RSTB) can be inverted is desired. 10 Lattice Semiconductor Pseudo Dual-Port SRAM Mode ispXPLD 5000MX Family Data Sheet In Pseudo Dual-Port SRAM Mode the multi-function array is configured as a SRAM with an independent read and write ports that access the same 16,384-bits of memory. Data widths of 1, 2, 4, 8, 16 and 32 are supported by the MFB. Figure 10 shows the block diagram of the Pseudo Dual-Port SRAM. Write data, write address, chip select and write enable signals are always synchronous (registered). The read data and read address signals can be synchronous or asynchronous. Reset is asynchronous. All write signals share the same clock, and clock enable. All read signals share the same clock and clock enable. Reset is shared by both read and write signals. Table 6 shows the possible sources for the clock, clock enable and initialization signals for the various registers. Figure 10. Pseudo Dual-Port SRAM Block Diagram CLK0 CLK1 CLK2 CLK3 RESET Read Address (RAD[0:8-13]) Read Data (RD[0:0-15]) Write Address (WAD[0:8-13]) 68 Inputs From Routing 16,384 bit Pseudo ` Dual Write Enable (WE) ` Port Write Clock (WCLK) SRAM Write Chip Sel (WCS[0,1]) Array (WD[0:0,1,3,7,15,31]) Write Data Write Clk Enable (WCEN) Read Clk Enable (RCEN) Read Clock (RCLK) Reset (RST) Table 6. Register Clock, Clock Enable, and Reset in Pseudo Dual-Port SRAM Mode Register Input Clock Write Address, Write Clock Enable Data, Write Enable, and Write Chip Select Reset Clock Read Data and Read Clock Enable Address Reset Source WCLK or one of the global clocks (CLK0 - CLK3). The selected signal can be inverted if desired. WCEN or one of the global clocks (CLK1 - CLK2). The selected signal can be inverted if desired. Created by the logical OR of the global reset signal and RST. RST may have inversion if desired. RCLK or one of the global clocks (CLK0 - CLK3). The selected signal can be inverted if desired. RCEN or one of the global clocks (CLK1 - CLK2). The selected signal can be inverted if desired. Created by the logical OR of the global reset signal and RST. RST may have inversion if desired. 11 Lattice Semiconductor Single-Port SRAM Mode ispXPLD 5000MX Family Data Sheet In Single-Port SRAM Mode the multi-function array is configured as a single-port SRAM. In this mode one ports accesses 16,384-bits of memory. Data widths of 1, 2, 4, 8, 16 and 32 are supported by the MFB. Figure 11 shows the block diagram of the single-port SRAM. Write data, address, chip select and read/write signals are always synchronous (registered.) The output data signals can be synchronous or asynchronous. Reset is asynchronous. All signals share a common clock, clock enable, and reset. Table 7 shows the possible sources for the clock, clock enable and reset signals. Figure 11. Single-Port SRAM Block Diagram CLK0 CLK1 CLK2 CLK3 RESET Read/Write Address (AD[0-8:13]) Read Data (DO[0-0,31]) Write Data (DI[0-0,1,3,7,15,31]) Write/Read (WR) 68 Inputs from Routing Clock (CLK) Chip Select Reset (RST) (CS0,1) 16,384-Bit ` `SRAM Array Clk Enable (CEN) Table 7. Register Clock, Clock Enable, and Reset in Single-Port SRAM Mode Register Address, Write Data, Read Data, Read/ Write, and Chip Select Input Clock Clock Enable Reset Source CLK or one of the global clocks (CLK0 - CLK3). Each of these signals can be inverted if required. CEN or one of the global clocks (CLK1 - CLK 2). Each of these signals can be inverted if required. Created by the logical OR of the global reset signal and RST. RST is routed by the multifunction array from GRP, with inversion if desired. 12 Lattice Semiconductor FIFO Mode ispXPLD 5000MX Family Data Sheet In FIFO Mode the multi-function array is configured as a FIFO (First In First Out) buffer with built in control. The read and write clocks can be different or the same dependent on the application. Four flags show the status of the FIFO; Full, Empty, Almost Full, and Almost Empty. The thresholds for Full, Almost full and Almost empty are programmable by the user. It is possible to reset the read pointer, allowing support of frame retransmit in communications applications. If desired, the block can be used in show ahead mode allowing the early reading of the next read address. In this mode one ports accesses 16,384-bits of memory. Data widths of 1, 2, 4, 8, 16 and 32 are supported by the MFB. Figure 12 shows the block diagram of the FIFO. Write data, write enable, flag outputs and read enable are synchronous. The Write Data, Almost Full and Full share the same clock and clock enables. Read outputs are synchronous although these can be configured in look ahead mode. The Read Data, Empty and Almost Empty signals share the same clock and clock enables. Reset is shared by all signals. Table 8 shows the possible sources for the clock, clock enable and reset signals for the various registers. Figure 12. FIFO Block Diagram Write Enable (WE) Write Clock (WCLK) Reset (RST) CLK0 CLK1 CLK2 CLK3 RESET Read Clock (RCLK) Reset_RP (RSTRP) FIFO Control Logic FIFO Flags* Full, Empty, Almost Full, Almost Empty Read Enable (RE) `` 68 Inputs From Routing Write Data (DI[0:0-31]) 16,384-bit Read Data (DO[0:0-31]) SRAM Array *Control logic can be duplicated in adjacent MFB in 32-bit mode Table 8. Register Clocks, Clock Enables, and Initialization in FIFO Mode Register Input Source WCLK or one of the global clocks (CLK0 - CLK3). Each of these signals can be inverted if required. WE or one of the global clocks (CLK1 - CLK 2). Each of these signals can be inverted if required. N/A WCLK or one of the global clocks (CLK0 - CLK3). Each of these signals can be inverted if required. WE or one of the global clocks (CLK1 - CLK 2). Each of these signals can be inverted if required. Created by the logical OR of the global reset signal and RST. RST is routed by the multifunction array from GRP, with inversion if desired. RCLK or one of the global clocks (CLK0 - CLK3). Each of these signals can be inverted if required. RE or one of the global clocks (CLK1 - CLK 2). Each of these signals can be inverted if required. Created by the logical OR of the global reset signal and RST. RST is routed by the multifunction array from GRP, with inversion if desired. Write Data, Clock Write Enable Clock Enable Reset Full and Almost Full Flags Clock Clock Enable Reset Read Data, Clock Empty and Clock Almost Empty Enable Flags Reset 13 Lattice Semiconductor CAM Mode ispXPLD 5000MX Family Data Sheet In CAM Mode the multi-function array is configured as a Ternary Content Addressable Memory (CAM). CAM behaves like a reverse memory where the input is data and the output is an address. It can be used to perform a variety of high-performance look-up functions. As such, CAM has two modes of operation. In write or update mode the CAM behaves as a RAM and data is written to the supplied address. In read or compare operations data is supplied to the CAM and if this matches any of the data in the array the Match and Multiple Match (if there is more than one match) flags are set to true and the lowest address with matching data is output. The CAM contains 128 entries of 48 bits. Figure 13 shows the block diagram of the CAM. To further enhance the flexibility of the CAM a mask register is available. If enabled during updates, bits corresponding with those set to 1 in the mask register are not updated. If enabled during compare operations, bits corresponding to those set to 1 in the mask register are not included in the compare. A write don't care signal allows don't cares to be programmed into the CAM if desired. Like other write operations the mask register controls this. The write/comp data, write address, write enable, write chip select, and write don't care signals are synchronous. The CAM Output signals, match flag, and multimatch flag can be synchronous or asynchronous. The Enable mask register input is not latched but must meet setup and hold times relative to the write clock. All inputs must use the same clock and clock enable signals. All outputs must use the same clock and clock enable signals. Reset is common for both inputs and outputs. Table 9 shows the allowable sources for clock, clock enable, and reset for the various CAM registers. Figure 13. CAM Mode CLK0 CLK1 CLK2 CLK3 RESET Write/Comp Data (WD[0:31]) Write Address (WAD[0:6]) CAM Output CO[0:6] En Mask Reg (EN_MASK) Write Enable (WE) Write Chip Sel (WCS[0:1]) ` 68 Inputs From Routing ` 128X48 CAM Match Out MATCH WR Mask Reg (WR_MASK) WR don t care (WR_DC) Reset (RST) CLK (CLK) Clock Enable (CE) Multimatch Out MUL_MATCH Table 9. Register Clocks, Clock Enables, and Initialization in CAM Mode Register Write data, Write address, Enable mask register, Write enable, write chip select, and write don't care, CAM Output, Match, and Multimatch Input Clock Clock Enable Reset Source CLK or one of the global clocks (CLK0 - CLK3). Each of these signals can be inverted if required. WE or one of the global clocks (CLK1 - CLK 2). Each of these signals can be inverted if required. Created by the logical OR of the global reset signal and RST. RST is routed by the multifunction array from GRP, with inversion if desired 14 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet Clock Distribution The ispXPLD 5000MX family has four dedicated clock input pins: GCLK0-GCLK3. GLCK0 and GCLK3 can be routed through a PLL circuit or routed directly to the internal clock nets. The internal clock nets (CLK0-CLK3) are directly related to the dedicated clock pins (see Secondary Clock Divider exception when using the sysCLOCK circuit). These feed the registers in the MFBs. Note at each register there is the option of inverting the clock if required. Figure 14 shows the clock distribution network. Figure 14. Clock Distribution Network I/O/CLK_OUT0 GCLK0 VREF0 PLL0 SEC_OUT0 CLK_OUT0 CLK0 Clock Net To Macrocells CLK1 GCLK1 VREF1 sysCLOCK PLLs VREF2 GCLK2 CLK2 SEC_OUT1 PLL1 VREF3 GCLK3 CLK_OUT1 CLK3 Clock Net To Macrocells Global Clock Routing Clock Net To Macrocells Clock Net To Macrocells I/O/CLK_OUT1 sysCLOCK PLL The sysCLOCK PLL circuitry consists of Phase-Lock Loops (PLLs) and the various dividers, reset and feedback signals associated with the PLLs. This feature gives the user the ability to synthesize clock frequencies and generate multiple clock signals for routing within the device. Furthermore, it can generate clock signals that are deskewed either at the board level or the device level. The ispXPLD 5000MX devices provide two PLL circuits. PLL0 receives its clock inputs from GCLK 0 and provides outputs to CLK 0 (CLK 1 when using the secondary clock). PLL1 operates with signals from GCLK 3 and CLK 3 (CLK 2 when using the secondary clock). The optional outputs CLK_OUT can be routed to an I/O pin. The optional PLL_LOCK output is routed into the GRP. The optional input PLL_RST can be routed either from the GRP or directly from an I/O pin. The optional PLL_FBK into can be routed directly from a pin. Figure 15 shows the ispXPLD 5000MX PLL block diagram. Figure 16 shows the connection of optional inputs and outputs. 15 Lattice Semiconductor Figure 15. PLL Block Diagram ispXPLD 5000MX Family Data Sheet CLK_IN Input Clock (M) Divider Programable Delay PLL_RST VCO and Phase Detector Post-scalar (V) Divider CLK_OUT Clock Net PLL_LOCK Feedback Loop (N) Divider PLL_FBK Secondary Clock (K) Divider SEC_OUT Clock Net Figure 16. Connection of Optional PLL Inputs and Outputs To GRP PLL_LOCK CLK_OUT From Macrocell To GRP PLL_RST To GRP From Macrocell To GRP PLL_FBK I/O Pin* From Macrocell *See pinout table for details I/O Pin* I/O Pin* In order to facilitate the multiply and divide capabilities of the PLL, each PLL has dividers associated with it: M, N and K. The M divider is used to divide the clock signal, while the N divider is used to multiply the clock signal. The K divider is only used when a secondary clock output is needed. This divider divides the primary clock output and feeds to a separate global clock net. The V divider is used to provide lower frequency output clocks, while maintaining a stable, high frequency output from the PLL's VCO circuit. The PLL also has a delay feature that allows the output clock to be advanced or delayed to improve set-up and clock-to-out times for better performance. For more information on the PLL, please refer to Lattice technical note number TN1003, Lattice sysCLOCK PLL Usage Guidelines. 16 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet Output Sharing Array (OSA) A number of I/O pads are available in each sysIO bank to route the selected number of macrocells from the MFB outputs directly to the I/O pads in logic mode. In the ispXPLD 5000MX, the large number of inputs and PTs to the MFB as well as the presence of the PTSA can cover most routing flexibility of signals to I/O cells. The Output Sharing Array gives additional routing capability and I/O access to an MFB when a wide output function takes up the whole MFB and cannot be easily divided across multiple MFBs. By using the OSA, the wide output function, such as 32-bit FIFO, can have all of its output signals from the one MFB routed to I/O cells. In a given I/O block, the wide output functions must share the I/O pads with other logic functions. The OSA bypass option routes the MFB signal directly to the I/O cell, allowing a direct connection to the I/O cell. The logic functions use the option to provide faster speed to the outputs. The Logic Signal Connection tables list the OSA bypass as the primary macrocell and OSA options as alternate macrocells. Similarly, the Alternate Input listing in the table shows the alternate macrocell input connection for a given I/O pin. Figure 17 shows the alternate macrocell connections in an I/O cell. sysIO Banks The ispXPLD 5000MX devices are divided into four sysIO banks, consisting of multiple I/O cells, where each bank is capable of supporting 16 different I/O standards. Each sysIO bank has its own I/O voltage (VCCO) and reference voltage (VREF) resources allowing complete independence from the others. I/O Cell The I/O cell of the ispXPLD 5000MX devices contains an output enable (OE) MUX, a programmable tri-state output buffer, a programmable input buffer, and programmable bus-maintenance circuitry. The I/O cell receives inputs from its associated macrocells and the device pin. The I/O cell has a feedback line to its associated macrocells and a direct path to GRP. The output enable (OE) MUX selects the OE signal per I/O cell. The inputs to the OE MUX are the four global PTOE signals, PTOE and the two GOE signals. The OE MUX also has the ability to choose either the true or inverse of each of these signals. The output of the OE MUX goes through a logical AND with the TOE signal to allow easy tri-stating of the outputs for testing purposes. The MFBs are grouped into segments of four for the purpose of generating Shared PTOE signals. Each Shared PTOE signal is derived from PT 163 from one of the four MFBs. Table 10 shows the segments. The PTOE signal is derived from the first product term in each macrocell cluster, which is directly routed to the OE MUX. Therefore, every I/O cell can have a different OE signal. Figure 17 is a graphical representation of the I/O cell. 17 Lattice Semiconductor Figure 17. I/O Cell Shared PTOE 0 Shared PTOE 1 Shared PTOE 2 Shared PTOE 3 PTOE GOE0 GOE1 TOE Data Output from Primary Macrocell Data Output from Alternate Macrocells Output Sharing Array (OSA) To Adjacent I/O Pad Data Input to Routing To Primary Macrocell To Alternate Macrocell Delay Element ispXPLD 5000MX Family Data Sheet Output Buffer (VCCO Independent for Open Drain Outputs) VCCO for this Bank VCCO to All Other I/Os in Bank Differential Output Buffer CMOS/TTL Input Buffer (VREF Independent) GND I/O Pad + - VREF Dependent Input Buffer + - VREF to All other I/Os in Bank Differential I/O Buffer To Adjacent I/O Pad Table 10. Shared PTOE Segments Device ispXPLD 5256MX ispXPLD 5512MX ispXPLD 5768MX MFBs Associated With Segments (A, B, C, D) (E, F, G, H) (A, B, C, D) (E, F, G, H) (I, J, K, L) (M, N, O, P) (A, B, C, D) (E, F, G, H) (I, J, K, L) (M, N, O, P) (Q, R, S, T) (U, V, W, Z) (A, B, C, D) (E, F, G, H) (I, J, K, L) (M, N, O, P) (Q, R, S, T) (U, V, W, Z) (Y, Z, AA, AB) (AC, AD, AE, AF) ispXPLD 51024MX sysIO Standards Each I/O within a bank is individually configurable based on the VCCO and VREF settings. Some standards also require the use of an external termination voltage. Table 12 lists the sysIO standards with the typical values for VCCO, VREF and VTT. For more information on the sysIO capability, please refer to Lattice technical note number TN1000, sysIO Usage Guidelines for Lattice Devices, available at www.latticesemi.com. Table 11. Number of I/Os per Bank Device ispXPLD 5256MX ispXPLD 5512MX ispXPLD 5768MX ispXPLD 51024MX Maximum Number of I/Os per Bank (n) 36 68 96 96 18 Lattice Semiconductor Table 12. ispXPLD 5000MX Supported I/O Standards sysIO Standard LVTTL LVCMOS-3.3 LVCMOS-2.5 LVCMOS-1.8 PCI 3.3V AGP-1X SSTL3, Class I & II SSTL2, Class I & II CTT 3.3 CTT 2.5 HSTL, Class I HSTL, Class III HSTL, Class IV GTL+ LVPECL, Differential LVDS Nominal VCCO 3.3V 3.3V 2.5V 1.8V 3.3V 3.3V 3.3V 2.5V 3.3V 2.5V 1.5V 1.5V 1.5V N/A 2.5V, 3.3V 2.5V, 3.3V ispXPLD 5000MX Family Data Sheet Nominal VREF N/A N/A N/A N/A N/A N/A 1.5V 1.25V 1.5V 1.25V 0.75V 0.9V 0.9V 1.0V N/A N/A Nominal VTT N/A N/A N/A N/A N/A N/A 1.5V 1.25V 1.5V 1.25V 0.75V 0.75V 0.75V 1.5V N/A N/A Table 13. Differential Interface Standard Support1 sysIO Buffer LVDS LVPECL Driver Receiver Driver Receiver Supported Supported with standard termination Supported with external resistor network Supported with termination 1. For more information, refer to Lattice technical note TN1000, sysIO Usage Guidelines for Lattice Devices, available at www.latticesemi.com. Control, Clock, sysCONFIG and JTAG Signals Global clock pins support the same sysIO standards as general purpose I/O. When required the VREF signal is derived from the adjacent bank. When differential standards are supported two adjacent clock pins are paired to form the input. The TOE, PROGRAM, CFG0 and DONE pins of the ispXPLD 5000MX device are the only pins that do not have sysIO capabilities. The JTAG TAP pins support only LVCMOS 3.3, 2.5 and 1.8V standards. The voltage is controlled by VCCJ. These pins only support the LVTTL and LVCMOS standards applicable to the power supply voltage of the device. The global reset global output enable pins are associated with Bank 2 and support all of the sysIO standards. Hotsocketing The I/O on the ispXPLD 5000MX devices are well suited for those applications that require hot socketing capability, when configured as LVCMOS or LVTTL. Hot socketing a device requires that the device, when powered down, can tolerate active signals on the I/Os and inputs without being damaged. Additionally, it requires that the effects of the powered-down device be minimal on active signals. Programmable Drive Strength The drive strength of I/Os that are programmed as LVCMOS is tightly controlled and can be programmed to a variety of different values. Thus the impedance an output driver can be closely match to the characteristic impedance of the line it is driving. This allows users to eliminate the need for external series termination resistors. 19 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet Programmable Slew Rate The slew rate of outputs is carefully controlled. When outputs are configured as LVCMOS the devices support two slew rates. This allows system noise and performance to be balanced in a design. Programmable Bus-Maintenance All general-purpose inputs have programmable bus maintenance circuitry. These are intended to maintain a valid logic level into a device when driving devices go into the tri-state mode. Four options are available for users: pullup, pull-down, bus-keeper, or nothing. Expanded In-System Programmability (ispXP) The ispXPLD 5000MX family utilizes a combination of EEPROM non-volatile cells and SRAM technology to deliver a logic solution that provides "instant-on" at power-up, a convenient single chip solution, and the capability for infinite reconfiguration. A non-volatile array distributed within the device stores the device configuration. At power-up this information is transferred in a massively parallel fashion into SRAM bits that control the operation of the device. Figure 18 shows the different ports and modes that are used in the configuration and programming of the ispXPLD 5000MX devices. Figure 18. ispXP Block Diagram ISP 1149.1 TAP Port Port sysCONFIG Peripheral Port ISP Mode BACKGND 1532 sysCONFIG Programming in seconds Configuration in milliseconds Power-up E2CMOS Memory Space Memory Space Refresh Download in microseconds SRAM Memory Space IEEE 1532 ISP In-system programming of devices provides a number of significant benefits including rapid prototyping, lower inventory levels, higher quality and the ability to make in-field modifications. All ispXPLD 5000MX devices provide in-system programmability through their Boundary Scan Test Access Port. This capability has been implemented in a manner that ensures that the port remains compliant to the IEEE 1532 standard. By using IEEE 1532 as the communication interface through which ISP is achieved, customers get the benefit of a standard, well-defined interface. The IEEE1532 programming interface allows programming of either the non-volatile array or reconfiguration of the SRAM bits. The ispXPLD 5000MX devices can be programmed across the commercial temperature and voltage range. The PC-based Lattice software facilitates in-system programming of ispXPLD 5000MX devices. The software takes the JEDEC file output produced by the design implementation software, along with information about the scan chain, and creates a set of vectors used to drive the scan chain. The software can use these vectors to drive a scan chain via the parallel port of a PC. Alternatively, the software can output files in formats understood by common automated test equipment. This equipment can then be used to program ispXPLD 5000MX devices during the testing of a circuit board. 20 Lattice Semiconductor sysCONFIG Interface ispXPLD 5000MX Family Data Sheet In addition to being able to program the device through the IEEE 1532 interface a microprocessor style interface (sysCONFIG interface) allows reconfiguration of the SRAM bits within the device. For more information on the sysCONFIG capability, please refer to technical note number TN1026, ispXP Configuration Usage Guidelines. Security Scheme A programmable security scheme is provided on the ispXPLD 5000MX devices as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit prevents readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. The security bit also prevents programming and verification. The entire device must be erased in order to erase the security bit. Low Power Consumption The ispXPLD 5000MX devices use zero power non-volatile cells along with full CMOS design to provide low static power consumption. The 1.8V core reduces dynamic power consumption compared with devices with higher core voltages. For information on estimating power consumption, please refer to Lattice technical note number TN1031, Power Estimation in ispXPLD 5000MX Devices. Density Migration The ispXPLD 5000MX family has been designed to ensure that different density devices in the same package have compatible pin-outs. Furthermore, the architecture ensures a high success rate when performing design migration from lower density parts to higher density parts. In many cases, it is possible to shift a lower utilization design targeted for a high-density device to a lower density device. However, the exact details of the final resource utilization will impact the likely success in each case. IEEE 1149.1-Compliant Boundary Scan Testability All ispXPLD 5000MX devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic notes. Internal boundary scan registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be linked into a board-level serial scan path for board-level testing. The test access port has its own supply voltage and can operate with LVCMOS3.3, 2.5 and 1.8V standards. sysIO Quick Configuration To facilitate the most efficient board test, the physical nature of the I/O cells must be set before running any continuity tests. As these tests are fast, by nature, the overhead and time that is required for configuration of the I/Os' physical nature should be minimal so that board test time is minimized. The ispXPLD 5000MX family of devices allows this by offering the user the ability to quickly configure the physical nature of the sysIO cells. This quick configuration takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. Lattice's ispVMTM System programming software can either perform the quick configuration through the PC parallel port, or can generate the ATE or test vectors necessary for a third-party test system. 21 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet Absolute Maximum Ratings1, 2, 3 ispXPLD 5000MC 1.8V ispXPLD 5000MB/V 2.5V/3.3V Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . . . . . . . . -0.5 to 5.5V PLL Supply Voltage (VCCP) . . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . . . . . . . . -0.5 to 5.5V Output Supply Voltage (VCCO) . . . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . . . . . . . . -0.5 to 4.5V IEEE 1149.1 TAP Supply Voltage (VCCJ) . . . . . . . . -0.5 to 4.5V . . . . . . . . . . . . . . . . -0.5 to 4.5V Input Voltage Applied4, 5 . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V . . . . . . . . . . . . . . . . -0.5 to 5.5V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65 to 150C . . . . . . . . . . . . . . . -65 to 150C Junction Temperature (TJ) with Power Applied . . . -55 to 150C . . . . . . . . . . . . . . . -55 to 150C 1. Stress above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied (while programming, following the programming specifications). 2. Compliance with the Lattice Thermal Management document is required. 3. All voltages referenced to GND. 4. Overshoot and Undershoot of -2V to (VIHMAX +2) volts not to exceed 6V is permitted for a duration of <20ns. 5. A maximum of 64 I/Os per device with VIN > 3.6V is allowed. Recommended Operating Conditions Symbol VCC Parameter Supply Voltage for 1.8V Devices (ispXPLD 5000MC) Supply Voltage for 2.5V Devices (ispXPLD 5000MB) Supply Voltage for 3.3V Devices (ispXPLD 5000MV) PLL Block Supply Voltage for PLL 1.8V Devices VCCP PLL Block Supply Voltage for PLL 2.5V Devices PLL Block Supply Voltage for PLL 3.3V Devices TJ Junction Temperature (Commercial Operation) Junction Temperature (Industrial Operation) Min. 1.65 2.3 3 1.65 2.3 3 0 -40 Max. 1.95 2.7 3.6 1.95 2.7 3.6 90 105 Units V V V V V V C C E2CMOS Erase Reprogram Specifications Parameter Erase/Reprogram Cycle 1 Min. 1,000 Max. -- Units Cycles 1. Valid over commercial temperature range. Hot Socketing Characteristics1, 2, 3, 4 Symbol IDK 1. 2. 3. 4. Parameter Input or I/O Leakage Current Condition 0 VIN 3.0V Min. -- Typ. +/-50 Max. +/-800 Units A Insensitive to sequence of VCC and VCCO. However, assumes monotonic rise/fall rates for VCC and VCCO, provided (VIN - VCCO) 3.6V. 0 VCC VCC (MAX), 0 VCCO VCCO (MAX) IDK is additive to IPU, IPD or IBH. Device defaults to pull-up until non-volatile cells are active. LVTTL, LVCMOS only. 22 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet DC Electrical Characteristics Over Recommended Operating Conditions Symbol IIL, IIH1 IIH4 IPU3 IPD IBHLS IBHHS IBHLO IBHHO VBHT C1 C2 C3 Parameter Input or I/O Leakage Input High Leakage Current I/O Active Pullup Current I/O Active Pulldown Current Condition 0 VIN (VCCO - 0.2V) (VCCO - 0.2V) < VIN 3.6V 3.6V < VIN 5.5V and 3.0V VCCO 3.6V 0 VIN 0.7 VCCO VIL (MAX) VIN VIH (MAX) Min. -- -- -- -30 30 30 30 -- -- VCCO * 0.35 -- -- -- -- -- -- Typ. -- -- -- -- -- -- -- -- -- -- 8 8 8 8 8 8 Max. 10 40 3 -150 150 -- -- 150 150 VCCO * 0.65 -- -- -- -- -- -- Units A A mA A A A A A A A pf pf pf pf pf pf Bus Hold Low Sustaining Current VIN = VIL (MAX) Bus Hold High Sustaining Current VIN = 0.7 VCCO Bus Hold Low Overdrive Current 0 VIN VIH (MAX) Bus Hold High Overdrive Current Bus Hold Trip Points I/O Capacitance2 Clock Capacitance2 Global Input Capacitance2 0 VIN VIH (MAX) 0 VIN VIH (MAX) VCCO = 3.3V, 2.5V, 1.8V VCC = 1.8V, VIO = 0 to VIH (MAX) VCCO = 3.3V, 2.5V, 1.8V VCC = 1.8V, VIO = 0 to VIH (MAX) VCCO = 3.3V, 2.5V, 1.8V VCC = 1.8V, VIO = 0 to VIH (MAX) 1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is not measured with the output driver active. Bus maintenance circuits are disabled. 2. TA 25C, f=1.0MHz 3. IPU on JTAG pins has a maximum of -175A for 5512MX devices. 4. 5V tolerant inputs and I/Os should be placed in banks where 3.0V VCCO 3.6V. The JTAG and sysCONFIG ports are not included for the 5V tolerant interface. 23 Lattice Semiconductor Supply Current Symbol ispXPLD 5256 VCC = 3.3V, f = 1.0MHz ICC 1,2 ispXPLD 5000MX Family Data Sheet Parameter Condition Min. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ.3 26 26 16 4 4 3 11 11 3 1 1 1 33 33 22 4 4 3 11 11 3 1 1 1 40 40 30 4 4 3 11 11 3 1 1 1 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Units mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Operating Power Supply Current VCC = 2.5V, f = 1.0MHz VCC = 1.8V, f = 1.0MHz VCCO = 3.3V, f = 1.0MHz, unloaded VCCO = 2.5V, f = 1.0MHz, unloaded VCCO = 1.8V, f = 1.0MHz, unloaded VCCP = 3.3V, f = 10MHz VCCP = 2.5V, f = 10MHz VCCP = 1.8V, f = 10MHz VCCJ = 3.3V VCCJ = 2.5V VCCJ = 1.8V ICCO Standby Power Supply Current (per I/O Bank) ICCP PLL Power Supply Current (per PLL Bank) ICCJ Standby IEEE 1149.1 TAP Power Supply Current ispXPLD 5512 VCC = 3.3V, f = 1.0MHz ICC 1,2 Operating Power Supply Current VCC = 2.5V, f = 1.0MHz VCC = 1.8V, f = 1.0MHz VCCO = 3.3V, f = 1.0MHz, unloaded VCCO = 2.5V, f = 1.0MHz, unloaded VCCO = 1.8V, f = 1.0MHz, unloaded VCCP = 3.3V, f = 10MHz VCCP = 2.5V, f = 10MHz VCCP = 1.8V, f = 10MHz VCCJ = 3.3V VCCJ = 2.5V VCCJ = 1.8V ICCO Standby Power Supply Current (per I/O Bank) ICCP PLL Power Supply Current (per PLL Bank) ICCJ Standby IEEE 1149.1 TAP Power Supply Current ispXPLD 5768 VCC = 3.3V, f = 1.0MHz ICC 1,2 Operating Power Supply Current VCC = 2.5V, f = 1.0MHz VCC = 1.8V, f = 1.0MHz VCCO = 3.3V, f = 1.0MHz, unloaded VCCO = 2.5V, f = 1.0MHz, unloaded VCCO = 1.8V, f = 1.0MHz, unloaded VCCP = 3.3V, f = 10MHz VCCP = 2.5V, f = 10MHz VCCP = 1.8V, f = 10MHz VCCJ = 3.3V VCCJ = 2.5V VCCJ = 1.8V ICCO Standby Power Supply Current (per I/O Bank) ICCP PLL Power Supply Current (per PLL Bank) ICCJ Standby IEEE 1149.1 TAP Power Supply Current 24 Lattice Semiconductor Supply Current (Continued) Symbol ispXPLD 51024 VCC = 3.3V, f = 1.0MHz ICC1,2 Operating Power Supply Current VCC = 2.5V, f = 1.0MHz VCC = 1.8V, f = 1.0MHz ICCO Standby Power Supply Current (per I/O Bank) Parameter Condition ispXPLD 5000MX Family Data Sheet Min. -- -- -- -- -- -- -- -- -- -- -- -- Typ.3 75 75 55 4 4 3 11 11 3 1 1 1 Max. -- -- -- -- -- -- -- -- -- -- -- -- Units mA mA mA mA mA mA mA mA mA mA mA mA VCCO = 3.3V, f = 1.0MHz, unloaded VCCO = 2.5V, f = 1.0MHz, unloaded VCCO = 1.8V, f = 1.0MHz, unloaded VCCP = 3.3V, f = 10MHz VCCP = 2.5V, f = 10MHz VCCP = 1.8V, f = 10MHz VCCJ = 3.3V VCCJ = 2.5V VCCJ = 1.8V ICCP PLL Power Supply Current (per PLL Bank) ICCJ Standby IEEE 1149.1 TAP Power Supply Current 1. Device configured with 16-bit counters. 2. ICC varies with specific device configuration and operating frequency. 3. TA = 25C 25 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet sysIO Recommended Operating Conditions VCCO (V)2 Standard LVCMOS 3.3 LVCMOS 2.5 LVCMOS 1.81 LVTTL PCI 3.3 AGP-1X SSTL 2 SSTL 3 CTT 3.3 CTT 2.5 HSTL Class I HSTL Class III HSTL Class IV GTL+ LVDS Min. 3.0 2.3 1.65 3.0 3.0 3.15 2.3 3.0 3.0 2.3 1.4 1.4 1.4 1.4 2.3 Typ. 3.3 2.5 1.8 3.3 3.3 3.3 2.5 3.3 3.3 2.5 1.5 1.5 1.5 -- 2.5/3.3 Max. 3.6 2.7 1.95 3.6 3.6 3.45 2.7 3.6 3.6 2.7 1.6 1.6 1.6 3.6 3.6 Min. -- -- -- -- -- -- 1.15 1.3 1.35 1.35 0.68 -- -- 0.882 -- VREF (V) Typ. -- -- -- -- -- -- 1.25 1.5 1.5 1.5 0.75 0.9 0.9 1.0 -- Max. -- -- -- -- -- -- 1.35 1.7 1.65 1.65 0.9 -- -- 1.122 -- 1. Design tools default setting. 2. Inputs are independent of VCCO setting. However, VCCO must be set within the valid operating range for one of the supported standards. 26 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet sysIO Single Ended DC Electrical Characteristics Over Recommended Operating Conditions Input/Output Standard LVCMOS 3.3 VIL Min (V) -0.3 Max (V) 0.8 Min (V) 2.0 VIH Max (V) 5.5 VOL Max (V) 0.4 0.2 LVTTL -0.3 0.8 2.0 5.5 0.4 0.2 0.4 0.2 LVCMOS 1.8 1, 3 VOH Min (V) 2.4 VCCO - 0.2 2.4 VCCO - 0.2 VCCO - 0.4 VCCO - 0.2 VCCO - 0.4 VCCO -0.4 VCCO - 0.2 0.9 VCCO 0.9 VCCO VCCO - 1.1 VCCO - 0.9 VCCO - 0.62 VCCO - 0.43 VREF + 0.4 VREF + 0.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 n/a IOL2 (mA) IOH2 (mA) 20, 16, 12, -20, -16, -12, 8, 5.33, 4 -8, -5.33, -4 0.1 4 0.1 16, 12, 8, 5.33, 4 0.1 8 0.1 1.5 1.5 8 16 7.6 15.2 8 8 8 24 48 36 -0.1 -4 -0.1 -16, -12, -8, -5.33, -4 -0.1 -8 -0.1 -0.5 -0.5 -8 -16 -7.6 -15.2 -8 -8 -8 -8 -8 n/a LVCMOS 2.5 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 0.7 0.68 0.68 1.08 1.08 VREF - 0.2 VREF - 0.2 1.7 1.07 1.07 1.5 1.5 VREF + 0.2 VREF + 0.2 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 0.4 0.4 0.2 0.1 VCCO 0.1 VCCO 0.7 0.5 0.54 0.35 VREF - 0.4 VREF - 0.4 0.4 0.4 0.4 0.6 LVCMOS 1.83 PCI 3.34 AGP-1X4 SSTL3 class I SSTL3 class II SSTL2 class I SSTL2 class II CTT 3.3 CTT 2.5 HSTL class I HSTL class III HSTL class IV GTL+ 12, 5.33, 4 -12, -5.33, -4 VREF - 0.18 VREF + 0.18 VREF - 0.18 VREF + 0.18 VREF - 0.2 VREF - 0.3 VREF - 0.1 VREF - 0.2 VREF - 0.3 VREF - 0.2 VREF + 0.2 VREF + 0.2 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.2 1. Software default setting. 2. The average DC current drawn by I/Os between adjacent bank GND connections, or between the last GND in an I/O bank and the end of the I/O bank, as shown in the logic signals connection table, shall not exceed n*8mA. Where n is the number of I/Os between bank GND connections or between the last GND in a bank and the end of a bank. 3. For 1.8V devices (ispXPLD 5000MC) these specifications are VIL = 0.35 * VCC and VIH = 0.65 * VCC. 4. For 1.8V devices (ispXPLD 5000MC) these specifications are VIL = 0.3 * VCC * 3.3/1.8, VIH = 0.5 * VCC * 3.3/1.8. 27 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet sysIO Differential DC Electrical Characteristics Over Recommended Operating Conditions Parameter LVDS VINP VTHD IIN VOH VOL VOD VOD VOS VOS IOSD Input Voltage Differential Input Threshold Input Current Output High Voltage for VOP or VOM Output Low Voltage for VOP or VOM Output Voltage Differential Change in VOD Between High and Low Output Voltage Offset Change in VOS Between H and L Output Short Circuit Current VOD = 0V Driver outputs shorted (VOP - VOM)/2, RT = 100 Ohm 0.2 VCM 1.8V Power On RT = 100 Ohm RT = 100 Ohm (VOP - VOM), RT = 100 Ohm 0V +/-100mV -- -- 0.9V 250mV -- 1.125V -- -- -- -- -- 1.38V 1.03V 350mV -- 1.20V -- -- 2.4V -- +/-10uA 1.60V -- 450mV 50mV 1.375V 50mV 24mA Description Test Conditions Min. Typ. Max. LVPECL1 DC Parameter VCCO VIH VIL VOH VOL VDIFF 2 Parameter Description Input Voltage High Input Voltage Low Output Voltage High Output Voltage Low Differential Input voltage Min. 3.0 1.49 0.86 1.7 0.96 0.3 Max. 2.72 2.125 2.11 1.27 -- Min. 3.3 1.49 0.86 1.92 1.06 0.3 Max. 2.72 2.125 2.28 1.43 -- Min. 3.6 1.49 0.86 2.03 1.3 0.3 Max. 2.72 2.125 2.41 1.57 -- Units V V V V V V 1. These values are valid at the output of the source termination pack as shown above with 100-ohm differential load only (see Figure 19). The VOH levels are 200mV below the standard LVPECL levels and are compatible with devices tolerant of the lower common mode ranges. 2. Valid for 0.2 VCM 1.8V Figure 19. LVPECL Driver with Three Resistor Pack ispXPGA LVPECL Buffer 1/4 of Bourns P/N CAT 16-PC4F12 A Rs Zo to LVPECL differential receiver Rs Zo 28 RT=100 RD Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5000MX Family External Switching Characteristics 1, 2, 3 Over Recommended Operating Conditions -4 Parameter tPD tPD_PTSA tS tS_PTSA tSIR tH tH_PTSA tHIR tCO tR tRW tLPTOE/DIS tSPTOE/DIS tGOE/DIS tCW tGW tWIR tSKEW fMAX4 fMAX (Ext.) fMAX (Tog.) fMAX (CAMC)5 fMAX (CAM)5 Description Data Propagation Delay, 5-PT Bypass Data propagation delay MFB Register Setup Time Before Clock, 5-PT Bypass MFB Register Setup Time Before Clock MFB Register Setup Time Before Clock, Input Register Path MFB Register Hold Time Before Clock, 5-PT Bypass MFB Register Hold Time Before Clock MFB Register Hold Time Before Clock, Input Register Path MFB Register Clock-to-Output Delay External Reset Pin to Output Delay Reset Pulse Duration Input to Output Local Product Term Output Enable/Disable Input to Output Shared Product Term Output Enable/ Disable Global OE Input to Output Enable/Disable Clock Width, High or Low Gate Width Low (for Low Transparent) or High (for High Transparent) Input Register Clock Width, High or Low Clock-to-Out Skew, Block Level Clock Frequency with Internal Feedback Clock Frequency with External Feedback, 1/ (tS + tCO) Clock Frequency Max. Toggle Clock Frequency to CAM (Configure Mode) Clock Frequency to CAM (Compare Mode) Min. -- -- 2.2 2.5 1.0 0.0 0.0 0.5 -- -- 1.8 -- -- -- 1.5 1.5 1.5 -- -- -- -- -- -- Max. 4.0 4.8 -- -- -- -- -- -- 2.8 4.0 -- 6.0 6.0 4.5 -- -- -- 0.6 300 200 333 280 150 -45 Min. -- -- 2.8 3.1 1.0 0.0 0.0 0.5 -- -- 1.8 -- -- -- 1.5 1.5 1.5 -- -- -- -- -- -- Max. 4.5 5.7 -- -- -- -- -- -- 3.0 4.5 -- 7.0 7.0 5.5 -- -- -- 0.6 275 171 333 280 150 Min. -- -- 2.8 3.1 1.0 0.0 0.0 0.5 -- -- 1.8 -- -- -- 1.5 1.5 1.5 -- -- -- -- -- -- -5 Max. 5.0 6.0 -- -- -- -- -- -- 3.2 5.0 -- 7.5 7.5 5.5 -- -- -- 0.6 250 166 333 230 150 -52 Min. -- -- 3.0 3.6 0.5 0.0 0.0 1.0 -- -- 2.0 -- -- -- 1.8 1.8 1.8 -- -- -- -- -- -- Max. 5.2 6.5 -- -- -- -- -- -- 3.7 5.0 -- 8.5 8.5 6.5 -- -- -- 0.6 250 149 277 230 135 -75 Min. -- -- 4.5 5.5 1.7 0.0 0.0 1.3 -- -- 3.0 -- -- -- 2.5 2.5 2.5 -- -- -- -- -- -- Max. Units 7.5 9.5 -- -- -- -- -- -- 5.0 7.5 -- 10.5 10.5 7.5 -- -- -- 1.0 150 105 200 168 90 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz MHz MHz 29 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5000MX Family External Switching Characteristics (Continued)1, 2, 3 Over Recommended Operating Conditions -4 Parameter Description Clock Frequency to RAM in: fMAX (RAM)5 Single Port Mode Dual Port Mode Pseudo Dual Port Mode fMAX (FIFO)5 tPWR_ON 1. 2. 3. 4. 5. -45 Max. 155 155 180 225 200 Min. -- -- -- -- -- Max. 155 155 180 220 200 Min. -- -- -- -- -- -5 Max. 155 155 160 210 200 -52 Min. -- -- -- -- -- Max. 155 155 160 210 200 -75 Min. -- -- -- -- -- Max. Units 93 93 106 132 200 MHz MHz MHz MHz s Min. -- -- -- -- -- Clock Frequency to FIFO Power-on Time Timing v.1.8 Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate timing for other standards. Measured using standard switching circuit, global routing loading of 1, worst case PTSA loading and 1 output switching. Pulse widths and clock widths less than minimum will cause unknown behavior. Standard 16-bit counter using GRP feedback. CAM, FIFO, RAM fMAX specification used shared PT Clk. 30 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet Timing Model The task of determining timing in a ispXPLD 5000MX device is relatively simple. The timing model show in Figure 20 shows the specific delay paths. Once the implementation of a given function is determined either conceptually or from the software report file, the delay path of a function can easily be determined from the timing model. The Lattice design tools report the timing delays based on the same timing model. Note that internal timing parameters are for reference only, and are not tested. The external timing parameters are tested and guaranteed for every device. Figure 20. ispXPLD 5000MX Timing Model Diagram From Feedback t PDb Feedback tPDi t ROUTE tROUTEMF tBLA tCASC t INREG t INDIO t PTSA t EXP tCICOMFB tCICOMC tSUM DATA Q t ORP t BUF tIOO t EN t DIS OUT t FBK IN t IN tIOI Memory Functions tGCLK GCLK t GCLK _IN t IOI t PTCLK t BCLK C.E. t PLL _SEC_DELAY tPLL _DELAY t PTSR t BSR 3 CLK, CE and Reset Only S/R MC Reg. RST t RST tIOI OE t GOE tIOI Path only available for FIFO Flags t PTOE t SPTOE t GPTOE Some paths not available in memory mode. Refer to timing tables for details. 31 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5000MX Family Internal Switching Characteristics Over Recommended Operating Conditions Parameter In/Out Delays tIN tGCLK_IN tRST tGOE tBUF tEN tDIS Input Buffer Delay Global Clock Input Buffer Delay Global RESET Pin Delay Global OE Pin Delay Delay through Output Buffer Output Enable Time Output Disable Time Delay through SRP Input Buffer to Macrocell Register Delay Product Term Sharing Array Delay Internal Feedback Delay Global Clock Tree Delay Block PT Clock Delay Macrocell PT Clock Delay Programmable PLL Delay Increment Block PT Reset Delay Macrocell PT Set/ Reset Delay Macrocell PT OE Delay Segment PT OE Delay Output Sharing Array Delay Global PT OE Delay 5-PT Bypass Propagation Delay Macrocell Propagation Delay -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.70 0.40 3.77 1.98 1.16 2.52 1.92 -- -- -- -- -- -- -- 0.91 0.35 4.24 2.66 1.30 2.84 2.40 -- -- -- -- -- -- -- 0.96 0.35 4.71 2.34 1.45 3.16 2.40 -- -- -- -- -- -- -- 1.11 0.35 4.71 2.87 1.60 3.63 2.40 -- -- -- -- -- -- -- 1.30 0.55 7.07 3.27 2.17 4.23 3.60 ns ns ns ns ns ns ns Description Base Parameter -4 -45 -5 -52 -75 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Routing Delays tROUTE tINREG tPTSA tFBK tGCLK tBCLK tPTCLK tPLL_DELAY tBSR tPTSR tLPTOE tSPTOE tOSA tPTOE tPDB tPDI -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.95 0.60 0.50 0.19 0.52 0.12 0.12 0.30 0.72 0.60 0.83 0.83 0.80 0.83 0.20 0.50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2.06 0.60 0.50 0.02 0.32 0.14 0.14 0.30 0.81 0.75 1.19 1.19 0.90 1.04 0.23 0.93 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2.34 0.60 0.53 0.39 0.72 0.15 0.15 0.30 0.90 0.75 1.04 1.04 1.00 1.04 0.25 0.72 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2.24 0.47 0.83 0.03 0.82 0.15 0.15 0.30 0.94 0.75 1.52 1.52 1.00 1.04 0.25 0.72 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 3.66 1.63 1.34 0.60 0.78 0.23 0.23 0.30 1.35 1.13 1.31 1.31 1.50 1.56 0.38 1.04 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 32 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5000MX Family Internal Switching Characteristics (Continued) Over Recommended Operating Conditions Parameter Registered Delays tS tS_PT tH tCOi tCESi tCEHi tSIR D-Register Setup Time, Global Clock D-Register Setup Time, PT Clock D-Register Hold Time Register Clock to OSA Time Clock Enable Setup Time Clock Enable Hold Time D-Input Register Setup Time, Global Clock D-Input Register Setup Time, PT Clock D-Input Register Hold Time, Global Clock D-Input Register Hold Time, PT Clock Latch Setup Time, Global Clock Latch Setup Time, PT Clock Latch Hold Time Latch Gate to OSA Time Propagation Delay through Latch to OSA Transparent Asynchronous Reset or Set to OSA Delay Asynchronous Reset or Set Recovery Delay through SRP when Implementing Memory Functions -- -- -- -- -- -- -- 0.28 -0.13 1.90 -- 1.07 0.00 0.66 -- -- -- 0.72 -- -- -- 0.31 -0.11 2.56 -- 1.20 0.00 0.20 -- -- -- 1.03 -- -- -- 0.35 -0.10 2.50 -- 1.33 0.00 0.53 -- -- -- 0.68 -- -- -- 0.55 -0.10 2.40 -- 1.33 0.00 0.12 -- -- -- 0.93 -- -- -- 0.52 -0.07 4.00 -- 2.00 0.00 0.08 -- -- -- 1.50 -- -- -- ns ns ns ns ns ns ns Description Base Parameter -4 -45 -5 -52 -75 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units tSIR_PT -- 0.42 -- 0.37 -- 0.34 -- 0.34 -- 0.22 -- ns tHIR -- 0.84 -- 1.31 -- 1.01 -- 1.41 -- 2.91 -- ns tHIR_PT -- 0.00 -- 0.00 -- 0.00 -- 0.00 -- 0.00 -- ns Latched Delays tSL tSL_PT tHL tGOi tPDLi -- -- -- -- -- 0.18 0.18 -0.06 -- -- -- -- -- 0.07 0.52 0.00 0.00 0.00 -- -- -- -- -- 0.08 0.58 0.00 0.00 0.00 -- -- -- -- -- 0.08 0.65 0.00 0.00 0.00 -- -- -- -- -- 0.08 0.65 0.00 0.34 -0.03 -- -- -- -- -- 0.13 0.97 ns ns ns ns ns Reset and Set Delays tSRi -- -- 0.23 -- 0.26 -- 0.29 -- 0.29 -- 0.43 ns tSRR -- -- 0.42 -- 0.47 -- 0.53 -- 0.55 -- 0.79 ns eXtended Function Routing Delays tROUTEMF -- -- 2.00 -- 2.25 -- 2.51 -- 2.61 -- 3.76 ns 33 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5000MX Family Internal Switching Characteristics (Continued) Over Recommended Operating Conditions Parameter tCASC tCICOMFB tCICOMC Description Additional Delay for PT Cascading between MFBs Carry Chain Delay, MFB to MFB Carry Chain Delay, Macro-Cell to Macro-Cell Routing Delay for Extended Function Flags Additional Flag Delay when Expanding Data Widths Counter Sum Delay Block Loading Adder PT Expander Adder Additional Delay for the Input Register Secondary PLL Output Delay MFB Input Extender Input Buffer Selection Adder Output Buffer Selection Adder Write Data Setup before Write Clock Time Write Data Hold after Write Clock Time Opposite Clock Cycle Delay Write Clock to Full Flag Delay Write Clock to Almost Full Flag Delay Read Clock to Empty Flag Delay Read Clock to Almost Empty Flag Delay Base Parameter -- -- -- -4 -45 -5 -52 -75 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units -- -- -- 0.71 0.35 0.10 -- -- -- 0.80 0.39 0.11 -- -- -- 0.89 0.44 0.13 -- -- -- 0.92 0.46 0.13 -- -- -- 1.33 0.66 0.19 ns ns ns tFLAG -- tFLAGFULL, tFLAGAFULL, tFLAGEMPTY, tFLAGAEMPTY tPTSA -- 2.62 -- 2.94 -- 3.27 -- 3.40 -- 4.91 ns tFLAGEXP tSUM -- -- 2.57 0.80 -- -- 2.89 0.90 -- -- 3.21 1.00 -- -- 3.34 1.04 -- -- 4.82 1.50 ns ns Optional Adjusters tBLA tEXP tINDIO tPLL_SEC_DELAY tINEXP tROUTE tROUTE tINREG tPLL_DELAY tROUTE tGCLK_IN, tIN, tGOE, tRST tBUF -- -- -- -- -- 0.04 0.53 0.50 0.91 0.62 -- -- -- -- -- 0.04 0.60 0.56 0.91 0.70 -- -- -- -- -- 0.05 0.66 0.63 0.91 0.78 -- -- -- -- -- 0.05 0.69 0.65 0.91 0.81 -- -- -- -- -- 0.07 0.99 0.94 0.91 1.16 ns ns ns ns ns Input and Output Buffer Delays tIOI tIOO FIFO tFIFOWCLKS -- -0.27 -- -0.27 -- -0.22 -- -0.22 -- -0.21 -- ns ns Refer to sysIO Adjuster Tables ns tFIFOWCLKH tFIFOCLKSKEW tFIFOFULL tFIFOAFULL tFIFOEMPTY tFIFOAEMPTY -- -- -- -- -- -- -0.01 -- -- -- -- -- -- 1.40 3.08 3.08 3.08 3.08 -0.01 -- -- -- -- -- -- 1.40 3.08 3.08 3.08 3.08 -0.01 -- -- -- -- -- -- 1.76 3.85 3.86 3.86 3.86 -0.01 -- -- -- -- -- -- 1.76 3.85 3.86 3.86 3.86 -0.01 -- -- -- -- -- -- 1.83 4.00 4.01 4.01 4.01 ns ns ns ns ns ns 34 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5000MX Family Internal Switching Characteristics (Continued) Over Recommended Operating Conditions Parameter tFIFOWES tFIFOWEH tFIFORES tFIFOREH tFIFORSTO tFIFORSTR tFIFORSTPW tFIFORCLKO Description Write-Enable setup before Write Clock Write-Enable hold after Write Clock Read-Enable setup before Read Clock Read-Enable hold after Read Clock Reset to Output Delay Reset Recovery Time Reset Pulse Width Read Clock to FIFO Out Delay Memory Select Setup before CLK Memory Select Hold after CLK Enable Mask Register Setup Time before CLK Enable Mask Register Setup Time after CLK Address Setup Time before Clock Address Hold Time after Clock Data Setup Time before Clock Data Hold Time after Clock "Don't Care" Setup Time before Clock "Don't Care" Hold Time after Clock R/W Setup Time before Clock R/W Enable Hold Time after Clock Clock Enable Setup Time before Clock Clock Enable Hold Time after Clock Base Parameter -- -- -- -- -- -- -- -- -4 -45 -5 -52 -75 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 2.33 -2.95 2.69 -3.17 -- 1.20 0.14 -- -- -- -- -- 3.30 -- -- 3.73 2.33 -2.95 2.35 -3.17 -- 1.20 0.14 -- -- -- -- -- 3.30 -- -- 3.73 2.91 -2.36 2.79 -2.53 -- 1.50 0.18 -- -- -- -- -- 4.13 -- -- 4.66 2.91 -2.36 2.38 -2.53 -- 1.50 0.18 -- -- -- -- -- 4.13 -- -- 4.66 3.03 -2.27 4.14 -2.44 -- 1.56 0.19 -- -- -- -- -- 4.29 -- -- 4.84 ns ns ns ns ns ns ns ns CAM - Update Mode tCAMMSS tCAMMSH tCAMENMSKS -- -- -- 1.40 -0.01 -0.27 -- -- -- 0.70 -0.01 -0.27 -- -- -- 1.50 -0.01 -0.22 -- -- -- 1.40 -0.01 -0.22 -- -- -- 1.44 -0.01 -0.21 -- -- -- ns ns ns tCAMENMSKH tCAMADDS tCAMADDH tCAMDATAS tCAMDATAH tCAMDCS tCAMDCH tCAMRWS tCAMRWH tCAMCES tCAMCEH -- -- -- -- -- -- -- -- -- -- -- -0.01 -0.27 -0.01 -0.41 -0.01 -0.27 -0.01 -0.27 -0.01 1.55 -2.95 -- -- -- -- -- -- -- -- -- -- -- -0.01 -0.27 -0.01 -0.41 -0.01 -0.27 -0.01 -0.27 -0.01 1.55 -2.95 -- -- -- -- -- -- -- -- -- -- -- -0.01 -0.22 -0.01 -0.33 -0.01 -0.22 -0.01 -0.22 -0.01 1.94 -2.36 -- -- -- -- -- -- -- -- -- -- -- -0.01 -0.22 -0.01 -0.33 -0.01 -0.22 -0.01 -0.22 -0.01 1.94 -2.36 -- -- -- -- -- -- -- -- -- -- -- -0.01 -0.21 -0.01 -0.31 -0.01 -0.21 -0.01 -0.21 -0.01 2.02 -2.27 -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns 35 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5000MX Family Internal Switching Characteristics (Continued) Over Recommended Operating Conditions Parameter tCAMWMSKS Description Write Mask Register Setup Time before Clock Write Mask Register Setup Time after Clock Reset to CAM Output Delay Reset Recovery Time Reset Pulse Width Data Setup Time before Clock Data Hold Time after Clock Enable Mask Register Setup Time before Clock Enable Mask Register Setup Time after Clock CAM Width Expansion Delay Clock to Output (Address Out) Delay Clock to Match Flag Delay Clock to MultiMatch Flag Delay CAM Reset to Flags Delay Address to Data Delay Memory Select Setup Before Clock Time Memory Select Hold time after Clock Time Clock Enable Setup before Clock Time Clock Enable Hold time after Clock Time Address Setup before Clock Time Base Parameter -- -4 -45 -5 -52 -75 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units -0.27 -- -0.27 -- -0.22 -- -0.22 -- -0.21 -- ns tCAMWMSKH tCAMRSTO tCAMRSTR tCAMRSTPW -- -- -- -- -0.01 -- 1.20 0.14 -- 3.30 -- -- -0.01 -- 1.20 0.14 -- 3.30 -- -- -0.01 -- 1.50 0.18 -- 4.13 -- -- -0.01 -- 1.50 0.18 -- 4.13 -- -- -0.01 -- 1.56 0.19 -- 4.29 -- -- ns ns ns ns CAM - Compare Mode tCAMDATAS tCAMDATAH tCAMENMSKS -- -- -- -0.41 -0.01 -0.27 -- -- -- -0.41 -0.01 -0.27 -- -- -- -0.33 -0.01 -0.22 -- -- -- -0.33 -0.01 -0.22 -- -- -- -0.31 -0.01 -0.21 -- -- -- ns ns ns tCAMENMSKH tCAMCASC tCAMCO tCAMMATCH tCAMMMATCH tCAMRSTFLAG -- -- -- -- -- -- -0.01 -- -- -- -- -- -- 0.40 6.19 6.19 5.50 3.16 -0.01 -- -- -- -- -- -- 0.40 6.13 6.13 5.50 3.16 -0.01 -- -- -- -- -- -- 0.50 6.81 6.07 6.38 3.95 -0.01 -- -- -- -- -- -- 0.50 6.61 6.61 6.38 3.95 -0.01 -- -- -- -- -- -- 0.51 9.63 10.22 7.72 4.11 ns ns ns ns ns ns Single Port RAM tSPADDDATA tSPMSS -- -- -- -0.27 5.97 -- -- -0.27 5.97 -- -- -0.27 5.97 -- -- -0.27 5.97 -- -- -0.21 7.76 -- ns ns tSPMSH tSPCES tSPCEH tSPADDS -- -- -- -- -0.01 2.30 -2.95 -0.27 -- -- -- -- -0.01 2.30 -2.95 -0.27 -- -- -- -- -0.01 2.30 -2.95 -0.27 -- -- -- -- -0.01 2.30 -2.95 -0.27 -- -- -- -- -0.01 9.80 -2.27 -0.21 -- -- -- -- ns ns ns ns 36 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5000MX Family Internal Switching Characteristics (Continued) Over Recommended Operating Conditions Parameter tSPADDH tSPRWS tSPRWH tSPDATAS tSPDATAH tSPCLKO tSPRSTO tSPRSTR tSPRSTPW Description Address Hold time after Clock Time R/W Setup before Clock Time R/W Hold time after Clock Time Data Setup before Clock Time Data Hold time after Clock Time Clock to Output Delay Reset to RAM Output Delay Reset Recovery Time Reset Pulse Width Memory Select Setup Before Clock Memory Select Hold time after Clock Clock Enable Setup before Read Clock Time Clock Enable Hold time after Read Clock Time Clock Enable Setup before Write Clock Time Clock Enable Hold time after Write Clock Time Read Address Setup before Read Clock Time Read Address Hold after Read Clock Time Write Address Setup before Write Clock Time Write Address Hold after Write Clock Time R/W Setup before Clock Time Base Parameter -- -- -- -- -- -- -- -- -- -4 -45 -5 -52 -75 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units -0.01 -0.27 -0.01 -0.27 -0.01 -- -- 1.20 0.14 -- -- -- -- -- 5.97 3.30 -- -- -0.01 -0.27 -0.01 -0.27 -0.01 -- -- 1.20 0.14 -- -- -- -- -- 5.97 3.30 -- -- -0.01 -0.27 -0.01 -0.27 -0.01 -- -- 1.20 0.14 -- -- -- -- -- 5.97 3.30 -- -- -0.01 -0.27 -0.01 -0.27 -0.01 -- -- 1.20 0.14 -- -- -- -- -- 5.97 3.30 -- -- -0.01 -0.21 -0.01 -0.21 -0.01 -- -- 1.56 0.19 -- -- -- -- -- 9.86 4.29 -- -- ns ns ns ns ns ns ns ns ns Pseudo Dual Port RAM tPDPMSS tPDPMSH -- -- -0.27 -0.01 -- -- -0.27 -0.01 -- -- -0.22 -0.01 -- -- -0.22 -0.01 -- -- -0.21 -0.01 -- -- ns ns tPDPRCES -- 2.33 -- 2.33 -- 2.91 -- 2.91 -- 3.03 -- ns tPDPRCEH -- -2.95 -- -2.95 -- -2.36 -- -2.36 -- -2.27 -- ns tPDPWCES -- 1.87 -- 1.87 -- 2.34 -- 2.34 -- 2.43 -- ns tPDPWCEH -- -2.95 -- -2.95 -- -2.36 -- -2.36 -- -2.27 -- ns tPDPRADDS -- -0.27 -- -0.27 -- -0.22 -- -0.22 -- -0.21 -- ns tPDPRADDH -- -0.01 -- -0.01 -- -0.01 -- -0.01 -- -0.01 -- ns tPDPWADDS -- -0.27 -- -0.27 -- -0.22 -- -0.22 -- -0.21 -- ns tPDPWADDH tPDPRWS -- -- -0.01 -0.27 -- -- -0.01 -0.27 -- -- -0.01 -0.22 -- -- -0.01 -0.22 -- -- -0.01 -0.21 -- -- ns ns 37 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5000MX Family Internal Switching Characteristics (Continued) Over Recommended Operating Conditions Parameter tPDPRWH tPDPDATAS tPDPDATAH tPDPRCLKO tPDPCLKSKEW tPDPRSTO tPDPRSTR tPDPRSTPW Dual Port RAM tDPMSAS Memory Select A Setup Before R/W A Time Memory Select Hold time after R/W A Time Clock Enable A Setup before Clock A Time Clock Enable A Hold time after Clock A Time Address A Setup before Clock A Time Address A Hold time after Clock A Time R/W A Setup before Clock A Time R/W A Hold time after Clock A Time Write Data A Setup before Clock A Time Write Data A Hold time after Clock A Time Memory Select B Setup Before R/W B Time Memory Select Hold time after R/W B Time -- -0.27 -- -0.27 -- -0.27 -- -0.27 -- -0.21 -- ns Description R/W Hold time after Clock Time Data Setup before Clock Time Data Hold time after Clock Time Read Clock to Output Delay Opposite Clock Cycle Delay Reset to RAM Output Delay Reset Recovery Time Reset Pulse Width Base Parameter -- -- -- -- -- -- -- -- -4 -45 -5 -52 -75 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units -0.01 -0.27 -0.01 -- 1.40 -- 1.20 0.14 -- -- -- 5.08 -- 3.30 -- -- -0.01 -0.27 -0.01 -- 1.40 -- 1.20 0.14 -- -- -- 5.02 -- 3.30 -- -- -0.01 -0.22 -0.01 -- 1.76 -- 1.50 0.18 -- -- -- 5.66 -- 4.13 -- -- -0.01 -0.22 -0.01 -- 1.76 -- 1.50 0.18 -- -- -- 5.45 -- 4.13 -- -- -0.01 -0.21 -0.01 -- 1.83 -- 1.56 0.19 -- -- -- 8.54 -- 4.29 -- -- ns ns ns ns ns ns ns ns tDPMSAH -- -0.01 -- -0.01 -- -0.01 -- -0.01 -- -0.01 -- ns tDPCEAS -- 3.72 -- 3.72 -- 3.72 -- 3.72 -- 4.84 -- ns tDPCEAH tDPADDAS tDPADDAH tDPRWAS tDPRWAH tDPDATAAS tDPDATAAH -- -- -- -- -- -- -- -2.95 -0.27 -0.01 -0.27 -0.01 -0.27 -0.01 -- -- -- -- -- -- -- -2.95 -0.27 -0.01 -0.27 -0.01 -0.27 -0.01 -- -- -- -- -- -- -- -2.95 -0.27 -0.01 -0.27 -0.01 -0.27 -0.01 -- -- -- -- -- -- -- -2.95 -0.27 -0.01 -0.27 -0.01 -0.27 -0.01 -- -- -- -- -- -- -- -2.27 -0.21 -0.01 -0.21 -0.01 -0.21 -0.01 -- -- -- -- -- -- -- ns ns ns ns ns ns ns tDPMSBS -- -0.27 -- -0.27 -- -0.27 -- -0.27 -- -0.21 -- ns tDPMSBH -- -0.01 -- -0.01 -- -0.01 -- -0.01 -- -0.01 -- ns 38 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5000MX Family Internal Switching Characteristics (Continued) Over Recommended Operating Conditions Parameter tDPCEBS Description Clock Enable B Setup before Clock B Time Clock Enable Hold B after Clock B Time Address B Setup before Clock B Time Address B Hold time after Clock B Time R/W B Setup before Clock B Time R/W B Hold time after Clock B Time Write Data B Setup before Clock B Time Write Data B Hold after Clock B Time Read Clock A to Output Delay Read Clock B to Output Delay Opposite Clock Cycle Delay Reset to RAM Output Delay Reset Recovery Time Reset Pulse Width Base Parameter -- -4 -45 -5 -52 -75 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 2.33 -- 2.33 -- 2.33 -- 2.33 -- 3.03 -- ns tDPCEBH tDPADDBS tDPADDBH tDPRWBS tDPRWBH tDPDATABS tDPDATABH tDPRCLKAO tDPRCLKBO tDPCLKSKEW tDPRSTO tDPRSTR tDPRSTPW -- -- -- -- -- -- -- -- -- -- -- -- -- -2.95 -0.27 -0.01 -0.27 -0.01 -0.27 -0.01 -- -- 1.40 -- 1.20 0.14 -- -- -- -- -- -- -- 5.97 5.16 -- 3.30 -- -- -2.95 -0.27 -0.01 -0.27 -0.01 -0.27 -0.01 -- -- 1.40 -- 1.20 0.14 -- -- -- -- -- -- -- 5.92 5.16 -- 3.30 -- -- -2.95 -0.27 -0.01 -0.27 -0.01 -0.27 -0.01 -- -- 1.40 -- 1.20 0.14 -- -- -- -- -- -- -- 5.86 5.16 -- 3.30 -- -- -2.95 -0.27 -0.01 -0.27 -0.01 -0.27 -0.01 -- -- 1.40 -- 1.20 0.14 -- -- -- -- -- -- -- 5.65 5.16 -- 3.30 -- -- -2.27 -0.21 -0.01 -0.21 -0.01 -0.21 -0.01 -- -- 1.83 -- 1.56 0.19 -- -- -- -- -- -- -- 9.86 6.71 -- 4.29 -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns Timing v.1.8 1. The PT-delay to clock of RAM/FIFO/CAM should be tBCLK instead of tPTCLK. 2. The PT-delay to set/reset of RAM/FIFO/CAM should be tBSR instead of tPTSR. 39 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5000MX Family Timing Adders Parameter tIOI Input Adjusters LVTTL_in LVCMOS_18_in LVCMOS_25_in LVCMOS_33_in AGP_1X_in CTT25_in CTT33_in GTL+_in HSTL_I_in HSTL_III_in HSTL_IV_in LVDS_in LVPECL_in PCI_in SSTL2_I_in SSTL2_II_in SSTL3_I_in SSTL3_II_in Using 3.3V TTL Using 1.8V CMOS Using 2.5V CMOS Using 3.3V CMOS Using AGP 1x Using CTT 2.5V Using CTT 3.3V Using GTL+ tIOIN tIOIN tIOIN tIOIN tIOIN tIOIN tIOIN tIOIN -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.0 0.0 0.0 0.0 1.0 1.0 1.0 0.5 0.5 0.6 0.6 0.5 0.5 1.0 0.5 0.5 0.6 0.6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.0 0.0 0.0 0.0 1.0 1.0 1.0 0.5 0.5 0.6 0.6 0.5 0.5 1.0 0.5 0.5 0.6 0.6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.0 0.0 0.0 0.0 1.0 1.0 1.0 0.5 0.5 0.6 0.6 0.5 0.5 1.0 0.5 0.5 0.6 0.6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.0 0.0 0.0 0.0 1.0 1.0 1.0 0.5 0.5 0.6 0.6 0.5 0.5 1.0 0.5 0.5 0.6 0.6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.0 0.0 0.0 0.0 1.0 1.0 1.0 0.5 0.5 0.6 0.6 0.5 0.5 1.0 0.5 0.5 0.6 0.6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description -4 -45 -5 -52 -75 Base Param. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Using HSTL 2.5V, tIOIN Class I Using HSTL 2.5V, tIOIN Class III Using HSTL 2.5V, tIOIN Class IV Using Low Voltage Differential tIOIN Signaling (LVDS) Using Low Voltage PECL Using PCI tIOIN tIOIN Using SSTL 2.5V, tIOIN Class I Using SSTL 2.5V, tIOIN Class II Using SSTL 3.3V, tIOIN Class I Using SSTL 3.3V, tIOIN Class II Using Slow Slew (LVTTL and LVCMOS Outputs Only) tIOO Output Adjusters - Output Signal Modifiers Slow Slew tIOBUF, tIOEN -- 0.9 -- 0.9 -- 0.9 -- 0.9 -- 0.9 ns tIOO Output Adjusters - Output Configurations LVTTL_out Using 3.3V TTL Drive tIOBUF, tIOEN, tIODIS -- 1.2 -- 1.2 -- 1.2 -- 1.2 -- 1.2 ns LVCMOS_18_4mA_out tIOBUF, Using 1.8V CMOS Standard, tIOEN, tIODIS 4mA Drive -- 0.3 -- 0.3 -- 0.3 -- 0.3 -- 0.3 ns Using 1.8V tIOBUF, LVCMOS_18_5.33mA_out CMOS Standard, tIOEN, tIODIS 5.33mA Drive -- 0.3 -- 0.3 -- 0.3 -- 0.3 -- 0.3 ns 40 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5000MX Family Timing Adders (Continued) Parameter LVCMOS_18_8mA_out Description -4 -45 -5 -52 -75 Base Param. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units -- 0.0 -- 0.0 -- 0.0 -- 0.0 -- 0.0 ns Using 1.8V tIOBUF, CMOS Standard, tIOEN, 8mA Drive tIODIS Using 1.8V tIOBUF, CMOS Standard, tIOEN, tIODIS 12mA Drive Using 2.5V tIOBUF, CMOS Standard, tIOEN, tIODIS 4mA Drive LVCMOS_18_12mA_out -- 0.0 -- 0.0 -- 0.0 -- 0.0 -- 0.0 ns LVCMOS_25_4mA_out -- 1.2 -- 1.2 -- 1.2 -- 1.2 -- 1.2 ns Using 2.5V tIOBUF, LVCMOS_25_5.33mA_out CMOS Standard, tIOEN, tIODIS 5.33 mA Drive LVCMOS_25_8mA_out Using 2.5V tIOBUF, CMOS Standard, tIOEN, tIODIS 8mA Drive Using 2.5V tIOBUF, CMOS Standard, tIOEN, tIODIS 12mA Drive Using 2.5V tIOBUF, CMOS Standard, tIOEN, tIODIS 16mA Drive Using 3.3V tIOBUF, CMOS Standard, tIOEN, tIODIS 4mA Drive -- 1.0 -- 1.0 -- 1.0 -- 1.0 -- 1.0 ns -- 0.4 -- 0.4 -- 0.4 -- 0.4 -- 0.4 ns LVCMOS_25_12mA_out -- 0.4 -- 0.4 -- 0.4 -- 0.4 -- 0.4 ns LVCMOS_25_16mA_out -- 0.4 -- 0.4 -- 0.4 -- 0.4 -- 0.4 ns LVCMOS_33_4mA_out -- 1.2 -- 1.2 -- 1.2 -- 1.2 -- 1.2 ns Using 3.3V tIOBUF, LVCMOS_33_5.33mA_out CMOS Standard, tIOEN, tIODIS 5.33mA Drive LVCMOS_33_8mA_out Using 3.3V tIOBUF, CMOS Standard, tIOEN, tIODIS 8mA Drive Using 3.3V tIOBUF, CMOS Standard, tIOEN, tIODIS 12mA Drive Using 3.3V tIOBUF, CMOS Standard, tIOEN, tIODIS 16mA Drive tIOBUF, Using 3.3V CMOS Standard, tIOEN, tIODIS 20mA Drive Using AGP 1x Standard Using CTT 2.5V tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS -- 1.2 -- 1.2 -- 1.2 -- 1.2 -- 1.2 ns -- 0.8 -- 0.8 -- 0.8 -- 0.8 -- 0.8 ns LVCMOS_33_12mA_out -- 0.6 -- 0.6 -- 0.6 -- 0.6 -- 0.6 ns LVCMOS_33_16mA_out -- 0.6 -- 0.6 -- 0.6 -- 0.6 -- 0.6 ns LVCMOS_33_20mA_out -- 0.3 -- 0.3 -- 0.3 -- 0.3 -- 0.3 ns AGP_1X_out -- 0.6 -- 0.6 -- 0.6 -- 0.6 -- 0.6 ns CTT25_out -- 0.3 -- 0.3 -- 0.3 -- 0.3 -- 0.3 ns CTT33_out Using CTT 3.3V -- 0.2 -- 0.2 -- 0.2 -- 0.2 -- 0.2 ns GTL+_out Using GTL+ -- 0.5 -- 0.5 -- 0.5 -- 0.5 -- 0.5 ns 41 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5000MX Family Timing Adders (Continued) Parameter HSTL_I_out Description -4 -45 -5 -52 -75 Base Param. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units -- 0.5 -- 0.5 -- 0.5 -- 0.5 -- 0.5 ns t Using HSTL 2.5V, IOBUF, tIOEN, Class I tIODIS t Using HSTL 2.5V, IOBUF, tIOEN, Class III tIODIS t Using HSTL 2.5V, IOBUF, tIOEN, Class IV tIODIS Using Low Voltage Differential Signaling (LVDS) Using Low Voltage PECL Using PCI Standard tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS HSTL_III_out -- 0.6 -- 0.6 -- 0.6 -- 0.6 -- 0.6 ns HSTL_IV_out -- 0.6 -- 0.6 -- 0.6 -- 0.6 -- 0.6 ns LVDS_out -- 0.8 -- 0.8 -- 0.8 -- 0.8 -- 0.8 ns LVPECL_out -- 0.3 -- 0.3 -- 0.3 -- 0.3 -- 0.3 ns PCI_out -- 0.6 -- 0.6 -- 0.6 -- 0.6 -- 0.6 ns SSTL2_I_out t Using SSTL 2.5V, IOBUF, tIOEN, Class I tIODIS t Using SSTL 2.5V, IOBUF, tIOEN, Class II tIODIS t Using SSTL 3.3V, IOBUF, tIOEN, Class I tIODIS t Using SSTL 3.3V, IOBUF, tIOEN, Class II tIODIS -- 0.3 -- 0.3 -- 0.3 -- 0.3 -- 0.3 ns SSTL2_II_out -- 0.5 -- 0.5 -- 0.5 -- 0.5 -- 0.5 ns SSTL3_I_out -- 0.2 -- 0.2 -- 0.2 -- 0.2 -- 0.2 ns SSTL3_II_out -- 0.4 -- 0.4 -- 0.4 -- 0.4 -- 0.4 ns Timing v.1.8 42 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet sysCLOCK PLL Timing Over Recommended Operating Conditions Symbol tPWH tPWL tR, tF tINSTB fMDIVIN fMDIVOUT fNDIVIN fNDIVOUT fVDIVIN fVDIVOUT tOUTDUTY Parameter Input clock, high time Input clock, low time Input Clock, rise and fall time Input clock stability, cycle to cycle (peak) M Divider input, frequency range M Divider output, frequency range N Divider input, frequency range N Divider output, frequency range V Divider input, frequency range V Divider output, frequency range Output clock, duty cycle Clean reference. 10 MHz < fMDIVOUT < 20 MHz or 100MHz < fVDIVIN < 160 MHz1 Clean reference. 20 MHz < fMDIVOUT < 320 MHz and 160MHz < fVDIVIN < 320 MHz1 Clean reference. 10 MHz < fMDIVOUT < 20 MHz or 100MHz < fVDIVIN < 160 MHz1 Clean reference. 20 MHz < fMDIVOUT < 320 MHz and 160MHz < fVDIVIN < 320 MHz1 Internal feedback External feedback Typical = +/- 250ps 80% to 80% 20% to 20% 20% to 80% Conditions Min 1.2 1.2 -- -- 10 10 10 10 100 10 40 -- Max -- -- 3.0 +/- 250 320 320 320 320 400 320 60 +/- 250 Units ns ns ns ps MHz MHz MHz MHz MHz MHz % ps tJIT(CC) Output clock, cycle to cycle jitter (peak) -- +/- 150 ps -- +/- 300 ps TJIT(PERIOD) 2 Output clock, period jitter (peak) -- -- -- -- +/- 150 3.0 600 25 ps ns ps us ps ns ns ns ns tCLK_OUT_DLY tPHASE tLOCK tPLL_DELAY tRANGE tPLL_RSTW tCLK_IN 3 Input clock to CLK_OUT delay Input clock to external feedback delta Time to acquire phase lock after input stable Delay increment (Lead/Lag) Total output delay range (lead/lag) Minimum reset pulse width Global clock input delay +/- 120 +/- 550 +/- 0.84 +/- 3.85 -- -- -- 1.8 1.0 1.5 tPLL_SEC_DELAY Secondary PLL output delay (tPLL_DELAY) 1. This condition assures that the output phase jitter will remain within specification. 2. Accumulated jitter measured over 10,000 waveform samples. 3. Internal timing for reference only. 43 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXP sysCONFIG Port Timing Specifications Symbol sysCONFIG Write Cycle Timing tSUCS tHCS tSUWD tHWD tPRGM tDINIT tIODISS tIOENSS tWH tWL fMAXW tHREAD tSUREAD tRH tRL fMAXR tCORD Input setup time of CS to CCLK rise Hold time of CS to CCLK rise Input setup time of write data to CCLK rise Hold time of write data to CCLK rise Low time to reset device SRAM INIT delay time User I/O disable User I/O enable Write clock High pulse width Write clock Low pulse width Write fMAX Hold time of READ to CCLK rise Input setup time of READ High to CCLK rise READ clock high pulse width READ clock low pulse width Read fMAX Clock to out for read data 10 1 10 0 5 -- -- -- 18 18 -- 1 15 18 18 -- -- -- -- -- -- 50 5 -- -- -- -- 27 -- -- -- -- 27 25 ns ns ns ns ns ms ns ns ns ns MHz ns ns ns ns MHz ns Timing Parameter Min. Max. Units sysCONFIG Read Cycle Timing 44 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet Boundary Scan Timing Specifications Over Recommended Operating Conditions Parameter tBTCP tBTCPH tBTCPL tBTS tBTH tBTRF tBTCO tBTCODIS tBTCOEN tBTCRS tBTCRH tBUTCO tBTUODIS tBTUPOEN TCK [BSCAN] clock pulse width TCK [BSCAN] clock pulse width high TCK [BSCAN] clock pulse width low TCK [BSCAN] setup time TCK [BSCAN] hold time TCK [BSCAN] rise/fall time TAP controller falling edge of clock to valid output TAP controller falling edge of clock to valid disable TAP controller falling edge of clock to valid enable BSCAN test capture register setup time BSCAN test capture register hold time BSCAN test update register, falling edge of clock to valid output BSCAN test update register, falling edge of clock to valid disable BSCAN test update register, falling edge of clock to valid enable Description Min 40 20 20 8 10 50 -- -- -- 8 10 -- -- -- Max -- -- -- -- -- -- 10 10 10 -- -- 25 25 25 Units ns ns ns ns ns mV/ns ns ns ns ns ns ns ns ns 45 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet Power Consumption ispXPLD 5000MC Typical ICC vs. Frequency 800 700 Max. ICC (mA) 600 500 400 300 200 100 0 0 100 200 400 Operating Frequency (MHz) Note: The device is configured with maximum number of 16-bit counters, no PLL, typical current at 1.8V, 25C. ispXPLD 5000MV/B Typical ICC vs. Frequency 800 51024V/B 51024MC Max. ICC (mA) 700 600 500 400 300 200 100 0 0 100 200 400 Operating Frequency (MHz) Note: The device is configured with maximum number of 16-bit counters, no PLL, typical current at 3.3V (MV) or 2.5V (MB), 25C. 5768MV/B 5768MC 5512MC 5256MC 5512V/B 5256V/B Power Estimation Coefficients DC Device ispXPLD 5256 ispXPLD 5512 ispXPLD 5768 ispXPLD 51024 K0 2.2 2.2 2.2 2.2 K1 8.4 8.4 8.4 8.4 K2 7 9.4 10.2 13 K3 12 18 21 27.6 K4 100 151 170 200 K5 K6 K7 6.476 6.476 6.476 6.476 ispXPLD 5000MC 16 17 27 35 ispXPLD 5000MV/B 24 25 36 43 0.1379 0.0433 0.1379 0.0433 0.1379 0.0433 0.1379 0.0433 Note: For further information about the use of these coefficients, refer to technical note TN1031, Power Estimation in ispXPLD 5000MX Devices. Memory Coefficients Device ispXPLD 5256 ispXPLD 5512 ispXPLD 5768 ispXPLD 51024 K8 0.004719 0.004719 0.004719 0.004719 K9 0.0924 0.0924 0.0924 0.0924 K10 4.4 4.4 4.4 4.4 K11 2.9 2.9 2.9 2.9 * * * * * * * * * * * * K0 = Current per MFB input (A/MHz) K1 = Current per Product Term (A/MHz) K2 = Current per GRP from MFB (A/MHz) K3 = Current per GRP from I/O (A/MHz) K4 = Global clock tree current (A/MHz) K5 = PLL digital (mA/MHz) K6 = PLL analog (mA/MHz) K7 = PLL analog baseline (mA) DC = Baseline current at 0Mhz (mA) K8 = CAM frequency component (mA/MHz) K9 = CAM DC component (mA) K10 = Current per row decoder (A/MHz) 46 Lattice Semiconductor * K11 = Current per column driver (A/MHz) ispXPLD 5000MX Family Data Sheet Power Estimation Equations ICC = ICC_DC + IMFB_CPLD + IMFB_ SRAM/PDPRAM/FIFO + IMFB_DPRAM + IMFB_CAM + IPLL_D ICC_DC Use the appropriate value for 5000MC (1.8V power supply) or 5000MV/B (2.5V/3.3V power supply) from the data sheet. IMFB_CPLD = ((K0 * CPLD MFB inputs + K1 * CPLD Logical Product Terms + K2 * CPLD GRP from MFB + K3 * CPLD GRP from IFB) * AF+ K4) * FREQ / 1000A/mA IMFB_CAM = CAM Memory MFBs * ((FREQ * K8) + K9) (CAM operating in typical mode) IMFB_ SRAM/PDPRAM/FIFO = (WR_ PERCENT * (K1 + WR_ PERCENT * 8 * K0 + K10 + K11) + RD_ PERCENT * (K1 + 128 * RD_PERCENT * K0 + 8 * OSW_PERCENT * K2)) * SRAM/PDPRAM/FIFO Memory MFBs * FREQ / 1000A/mA IMFB_ DPRAM = (WR_ PERCENT * (2 * K1 + 2 * WR_ PERCENT * 8 * K0 + K10 + K11) + RD_ PERCENT * (2 * K1 + 2 * 128 * RD_PERCENT * K0 + 8 * OSW_PERCENT * K2)) * DPRAM Memory MFBs * FREQ / 1000A/mA IPLL_D = K5 * PLL_FREQ * number of PLLs used. IPPL_D is the PLL digital component of the VCC supply current. Analog portion of PLL supply current consumption, from PLL power pin: IPLL_A = (K6 * PLL_FREQ + K7) * number of PLLs used Notes: * * * * * * * * ICC = Current consumption of VCC power supply (mA) ICC-DC = ICC DC component - Current consumption at 0Mhz (mA) IMFB_CPLD = CPLD (non-memory logic) current consumption (mA) IMFB_SRAM/PDPRAM/FIFO = Current consumption for SRAM, PDPRAM, and FIFO (mA) IMFB_DPRAM = Current consumption for DPRAM (mA) IMFB_CAM = Current consumption for CAM (mA) IPLL_D = PLL Current consumption of digital VCC power supply (mA) IPLL_A = PLL analog power pin current consumption (VCCP pin) 47 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet Switching Test Conditions Figure 21 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 14. Figure 21. Output Test Load, LVTTL and LVCMOS Standards VCCO R1 Device Output R2 CL* Test Point *CL includes test fixture and probe capacitance. Table 14. Test Fixture Required Components Test Condition Default LVCMOS 1.8 I/O (L -> H, H -> L) LVCMOS I/O (L -> H, H -> L) Default LVCMOS 1.8 I/O (Z -> H) Default LVCMOS 1.8 I/O (Z -> L) Default LVCMOS 1.8 I/O (H -> Z) Default LVCMOS 1.8 I/O (L -> Z) R1 106 -- -- 106 -- 106 R2 106 -- 106 -- 106 -- CL 35pF 35pF 35pF 35pF 5pF 5pF Timing Ref. VCCO/2 LVCMOS3.3 = 1.5V LVCMOS2.5 = VCCO/2 LVCMOS1.8 = VCCO/2 VCCO/2 VCCO/2 VOH - 0.15 VOL + 0.15 VCCO 1.8V LVCMOS3.3 = 3.0V LVCMOS2.5 = 2.3V LVCMOS1.8 = 1.65V 1.65V 1.65V 1.65V 1.65V Note: Output test conditions for all other interfaces are determined by the respective standards. 48 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet Signal Descriptions Signal Names TMS TCK TDI TDO TOE GOE0, GOE1 RESET Descriptions Input - This pin is the Test Mode Select input, which is used to control the IEEE 1149.1 state machine. Input - This pin is the Test Clock input pin, used to clock the IEEE 1149.1 state machine. Input - This pin is the IEEE 1149.1 Test Data in pin, used to load data. Output - This pin is the IEEE 1149.1 Test Data out pin used to shift data out. Input - Test Output Enable pin. TOE tristates all I/O pins when driven low. Input - Global output enable inputs. Input - This pin resets all the registers in the device. The global polarity (active high or active low) for this pin is selectable on a global basis. Input/Output - These are the general purpose I/O used by the logic array. y is the MFB reference (alpha) and z is the macrocell reference (numeric) y: A-X (768 macrocells) y: A-P (512 macrocells) y: A-H (256 macrocells) z: 0-31 GND - Ground No connect VCC - The power supply pins for core logic. VCC - The power supply pins for I/O banks 0, 1, 2, and 3. Input - This pin defines the reference voltage for I/O banks 0, 1, 2, and 3. Input - Global clock/clock enable inputs (see Figure 14 for differential pairing). Output - Optional clock output from PLL 0 and 1. Input - Optional input resets the M divider in PLL 0 and 1. Input - Optional feedback input for PLL 0 and 1. GND - Ground for PLLs. VCC - The power supply pin for PLLs. VCC - The power supply for the IEEE 1149.1 interface. I/O - sysCONFIG data pins, bit x. Input - sysCONFIG interface chip select. Drive low to select sysCONFIG interface. Input - Defines SRAM configuration mode. Low: sysCONFIG port, high: E2CMOS or IEEE 1149.1 TAP. Input - Controls the programming of SRAM. Hold high for normal operation. Toggle low to reload SRAM from E2 memory. Input - Clock for sysCONFIG interface. Reads and writes occur on the rising edge of the clock. Input - Drive high to perform reads from the sysCONFIG interface. I/O - Indicates status of configuration. Can be driven low to inhibit configuration. Output (open drain) - Indicates status of configuration. yzz GND NC VCC VCCO0, VCCO1, VCCO2, VCCO3 VREF0, VREF1, VREF2, VREF3 GCLK0, GCLK1, GCLK2, GCLK3 CLK_OUT0, CLK_OUT1 PLL_RST0, PLL_RST1 PLL_FBK0, PLL_FBK1 GNDP VCCP VCCJ DATAx CSB CFG0 PROGRAMB CCLK1 READ1 INITB DONE 1. These inputs should not toggle during power up for proper power-up configuration. 49 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5000MX Power Supply and NC Connections1 Signals VCC 208 PQFP4 256 fpBGA3, 5 484 fpBGA, 53 A17, A6, AA2, AA21, AB17, AB6, B2, B21, D19, D4, F1, F22, G10, G11, G12, G13, K16, K7, L16, L7, M16, M7, T10, T11, T12, T13, T14, T9, U1, U22, W19, W4 672 fpBGA3, 5 AA21, AA6, F21, F6, G20, G7, J13, J14, K13, K14, L13, L14, M13, M14, N10, N11, N12, N15, N16, N17, N18, N9, P10, P11, P12, P15, P16, P17, P18, P9, R13, R14, T13, T14, U13, U14, V13, V14, Y20, Y7 10, 49, 76, 114, D4, D13, F6, F11, L6, 153, 180 L11, N4, N13 VCCO0 VCCO1 VCCO2 5, 17, 189, 204 A1, F7, G6 42, 57, 72 85, 100, 107, 121 146, 161, 176 136 27 15, 29, 44, 81, 119, 148, 185, 7, 19, 191, 205, 40, 56, 70, 87, 101, 109, 123, 144, 160, 174 K6, L7, T1 K11, L10, T16 B9, C3, G8, G9, H7, J2, J7, P4 H10, H11, H8, H9, J8, J9, K8, L8, M8, N8 AA9, R7, T3, T8, Y3 AA14, R16, T15, T20, Y20 P8, R8, T8, U8, V8, V9, W10, W11, W8, W9 P19, R19, T19, U19, V18, V19, W12, W13, W14, W15, W16, W17, W18, W19 VCCO3 VCCP VCCJ GND A16, F10, G11 J16 J1 K1, C3, C14, E5, E12, G7, G8, G9, G10, H7, H8, H9, H10, J7, J8, J9, J10, K7, K8, K9, K10, M5, M12, P3 B14, C20, G14, G15, H16, J16, H12, H13, H14, H15, H16, H17, H18, J21, P19 H19, J18, J19, K19, L19, M19, N19 M22 M1 N1, A1, A2, A21, A22, AA1, AA22, AB1, AB22, B1, B22, C15, C8, D11, D12, E18, E5, F17, F6, G16, G7, H10, H11, H12, H13, H14, H15, H20, H3, H8, H9, J10, J11, J12, J13, J14, J15, J8, J9, K10, K11, K12, K13, K14, K15, K8, K9, L10, L11, L12, L13, L14, L15, L19, L4, L8, L9, M10, M11, M12, M13, M14, M19, M4, M9, N10, N11, N12, N13, N14, N9, P10, P11, P12, P13, P14, P9, R10, R11, R12, R13, R14, R15, R8, R9, T16, T7, W11, W12, Y15, Y8 N22 5512MX: P1, AA19, AB2, AB21, J17, J6, K1, K17, K18, K19, K2, K20, K21, K22, K3, K4, K5, K6, L1, L17, L18, L2, L20, L21, L22, L3, L5, L6, M15, M17, M18, M2, M20, M21, M3, M5, M6, M8, N15, N17, N18, N19, N2, N20, N21, N3, N4, N5, N6, N8, P15, P17, P18, P2, P21, P22, P5, P6, P8, U17, U6, V18, V5, W6 5768MX/51024MX: None N25 N4 A11, A16, A2, A25, AE1, AE2, AE25, AE26, AF11, AF16, AF2, AF25, B1, B2, B25, B26, J10, J11, J12, J15, J16, J17, K10, K11, K12, K15, K16, K17, K18, K9, L1, L10, L11, L12, L15, L16, L17, L18, L26, L9, M10, M11, M12, M15, M16, M17, M18, M9, N13, N14, P13, P14, R10, R11, R12, R15, R16, R17, R18, R9, T1, T10, T11, T12, T15, T16, T17, T18, T26, T9, U10, U11, U12, U15, U16, U17, U18, U9, V10, V11, V12, V15, V16, V17 GNDP NC 2 134 -- K16 5256MX: A2, A11, A12, A15, B2, B12, B15, B16, C4, C12, C15, C16, D1, D11, D14, D15, D16, E1, E4, E10, E11, E13, E14, F4, F5, F12, F13, L1, L4, M3, M7, M13, N2, N6, P1, P2, P5, P6, P13, P14, P15, P16, R1, R2, R4, R5, R6, R16, T2, T3, T4, T5, T6 5512MX/5768MX: L1 P26 A12, A13, A14, A15, AA10, AA11, AA12, AA13, AA14, AA15, AA16, AA17, AA7, AB10, AB11, AB12, AB13, AB14, AB15, AB16, AB17, AC10, AC11, AC12, AC13, AC14, AC15, AC16, AC17, AD11, AD12, AD13, AD14, AD15, AD16, AE11, AE12, AE13, AE14, AE15, AE16, AF12, AF13, AF14, AF15, B11, B12, B13, B14, B15, B16, C11, C12, C13, C14, C15, C16, C3, D10, D11, D12, D13, D14, D15, D16, D17, E10, E11, E12, E13, E14, E15, E16, E17, E6, E7, E8, F10, F11, F12, F13, F14, F15, F16, F17, G10, G11, G12, G13, G14, G15, G16, G17, Y10, Y11, Y12, Y13, Y14, Y15, Y16, Y17 1. All grounds must be electrically connected at the board level. 2. NC pins should not be connected to any active signals, VCC or GND. 3. Balls for GND, VCC and VCCOX are connected within the substrate to their respective common signals. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order ascending horizontally. 4. Pin orientation follows the conventional counter-clockwise order from pin 1 marking of the topside view. 5. Internal GNDs and I/O GNDs (Bank 0 - Bank 3) are connected inside package. VCCO balls connect to four power planes within the package, one each for VCCOX. 50 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5256MX Logic Signal Connections sysIO Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 LVDS Pair 61N 61P 62N 62P 63N 63P 64N 64P 65N 65P 66N 66P 67N 67P 68N 68P 69N 69P GCLK0P GCLK0N 0P 0N 1P 1N 2P 2N 3P 3N 4P Primary Macrocell/ Function H30 H28 H26 H24 H22 H21 VCC H20 H18/CLK_OUT0 H16 H14 GND H12 VCCO0 H10 GND (Bank 0) H8 H6/PLL_RST0 H5 H4/PLL_FBK0 H2 H0 GCLK0 VCCJ GCLK1 GND TDI TMS TCK TDO A0/DATA0 A2/DATA1 A4/DATA2 A5/DATA3 A6/DATA4 A8/DATA5 GND (Bank 1) A10/DATA6 VCCO1 A12/DATA7 GND A14/INITB Alternate Outputs Macrocell 1 G17 G16 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 A0 A1 A2 A3 A4 A5 A6 A7 A8 Macrocell 2 H17 H16 H15 H14 H13 H12 H11 H10 H9 H8 H7 H6 H5 H4 B0 B1 B2 B3 B4 B5 B6 B7 B8 Alternate Input H31 H29 H27 H25 H23 H19 H17 H15 H13 H11 H9 H7 H3 H1 A1 A3 A7 A9 A11 A13 A15 256 fpBGA Ball Number B1 C1 D3 C2 E3 D2 VCC E2 F2 F1 G1 GND F3 VCCO0 G5 GND (Bank 0) H5 G4 G3 H3 G2 H1 H2 See Power Supply and NC Connections Table J2 GND H6 H4 J6 K2 K3 J3 J5 J4 L2 M1 GND (Bank 1) K4 VCCO1 L3 GND K5 51 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5256MX Logic Signal Connections (Continued) sysIO Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 LVDS Pair 4N 5P 5N 6P 6N 7P 7N 8P 8N 9P 9N 10P 10N 11P 11N 12P 12N 13P 13N 14P 14N 15P 15N 16P 16N 17P 17N 18P 18N 19P 19N Primary Macrocell/ Function A16/CSB A18/READ A20/CCLK VCC DONE A22 A24 A26 A28 PROGRAMB GND (Bank 1) VCCO1 CFG0 B2 B4 B5 B6 B8 B10 B12 B14 B16/VREF1 B18 B20 GND (Bank 1) B21 VCCO1 B22 B24 B26 VCC B28 B30 C0 C2 C4 C5 C6 VCCO2 C8 GND (Bank 2) C10 C12 Alternate Outputs Macrocell 1 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 C0 C1 C2 C3 C4 C5 C6 C7 Macrocell 2 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 D0 D1 D2 D3 D4 D5 D6 D7 Alternate Input A17 A19 A21 A23 A25 A27 A29 B3 B7 B9 B11 B13 B15 B17 B19 B23 B25 B27 B29 B31 C1 C3 C7 C9 C11 C13 256 fpBGA Ball Number L5 N1 M2 VCC M4 N3 P4 N5 M6 R3 GND (Bank 1) VCC01 L8 T7 R7 N7 P7 T8 R8 M8 P8 L9 N8 M9 GND (Bank 1) N10 VCCO1 T9 T10 R9 VCC P9 N9 T11 T12 P10 R10 R11 VCCO2 M10 GND (Bank 2) M11 T13 52 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5256MX Logic Signal Connections (Continued) sysIO Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 LVDS Pair 20P 20N 21P 21N 22P 22N 23P 23N 24P 24N 25P 25N 26P 26N 27P 27N 28P 28N 29P 29N 30P 30N 31P 31N 32P 32N 33P 33N GCLK3N GCLK3P Primary Macrocell/ Function C14 C16/VREF2 C18 C20 C21 C22 C24 C26 C28 C30 VCCO2 GND (Bank 2) D0 D2 D4 D5 D6 D8 VCC D10 D12 D14 D16 GND D18 VCCO2 D20 GND (Bank 2) D21 D22 D24 D26 D28 D30 TOE RESET GOE0 GOE1 GNDP GCLK2 VCCP GCLK3 Alternate Outputs Macrocell 1 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 Macrocell 2 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 Alternate Input C15 C17 C19 C23 C25 C27 C29 C31 D1 D3 D7 D9 D11 D13 D15 D17 D19 D23 D25 D27 D29 D31 256 fpBGA Ball Number P11 T14 R12 R13 N11 T15 R14 N12 P12 R15 VCCO2 GND (Bank 2) N15 N14 N16 M16 M14 M15 VCC L13 L12 L15 L16 GND L14 VCCO2 K15 GND (Bank 2) K14 K12 K13 J13 J14 J12 J15 J11 H11 H13 See Power Supply and NC Connections Table H15 See Power Supply and NC Connections Table H16 53 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5256MX Logic Signal Connections (Continued) sysIO Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 LVDS Pair 34N 34P 35N 35P 36N 36P 37N 37P 38N 38P 39N 39P 40N 40P 41N 41P 42N 42P 43N 43P 44N 44P 45N 45P 46N 46P 47N 47P 48N 48P 49N 49P 50N 50P Primary Macrocell/ Function E30 E28 E26 E24/PLL_FBK1 E22/PLL_RST1 E21 GND (Bank 3) E20 VCCO3 E18 GND E16 E14 E12 E10/CLK_OUT1 VCC E8 E6 E5 E4 E2 E0 GND (Bank 3) VCCO3 F30 F28 F26 F24 F22 F21 F20 F18 F16/VREF3 F14 F12 F10 GND (Bank 3) F8 VCCO3 F6 F5 F4 VCC Alternate Outputs Macrocell 1 E27 E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16 E31 E30 E15 E14 E13 E12 E11 E10 E9 E8 E29 E28 E7 E6 E5 E4 E3 E2 Macrocell 2 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F31 F30 F15 F14 F13 F12 F11 F10 F9 F8 F29 F28 F7 F6 F5 F4 F3 F2 Alternate Input E31 E29 E27 E25 E23 E19 E17 E15 E13 E11 E9 E7 E3 E1 F31 F29 F27 F25 F23 F19 F17 F15 F13 F11 F9 F7 256 fpBGA Ball Number H14 G16 G15 F15 H12 G14 GND (Bank 3) F16 VCCO3 E16 GND G13 G12 F14 E15 VCC D12 B14 C13 A14 A13 B13 GND (Bank 3) VCCO3 B11 C11 B10 A10 C10 D10 C9 E9 D9 F9 A9 F8 GND (Bank 3) E8 VCCO3 A8 B9 D8 VCC 54 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5256MX Logic Signal Connections (Continued) sysIO Bank 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVDS Pair 51N 51P 52N 52P 53N 53P 54N 54P 55N 55P 56N 56P 57N 57P 58N 58P 59N 59P 60N 60P Primary Macrocell/ Function F2 F0 G30 G28 GND G26 G24 G22 VCCO0 G21 GND (Bank 0) G20 G18 G16/VREF0 G14 G12 G10 G8 G6 G5 G4 G2 G0 VCCO0 GND (Bank 0) Alternate Outputs Macrocell 1 E1 E0 G31 G30 G29 G28 G27 G26 G25 G24 G3 G2 G23 G22 G21 G20 G19 G18 G1 G0 Macrocell 2 F1 F0 H31 H30 H29 H28 H27 H26 H25 H24 H3 H2 H23 H22 H21 H20 H19 H18 H1 H0 Alternate Input F3 F1 G31 G29 G27 G25 G23 G19 G17 G15 G13 G11 G9 G7 G3 G1 256 fpBGA Ball Number B8 C8 B7 A7 NC D7 C7 B6 VCCO0 E7 GND (Bank 0) E6 A6 A5 A4 B5 A3 B4 B3 C5 C6 D5 D6 VCCO0 GND (Bank 0) Global Clock LVDS pair options: GCLK0 and GCLK1, as well as GCLK2 and GCLK3, can be paired together to receive differential clocks; where GCLK0 and GCLK3 are the positive LVDS inputs 55 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5512MX Logic Signal Connections sysIO Bank 0 0 0 0 0 -- 0 -- 0 0 0 0 0 0 0 0 0 -- 0 -- 0 0 0 -- 0 0 0 0 0 -- 0 -- 0 -- 0 0 0 0 0 0 -- -- LVDS Pair 109N 109P 110N 110P 111N -- 111P -- 112N 112P 113N 113P 114N 114P 115N 115P 116N -- 116P -- 117N 117P 118N -- 118P 119N 119P 120N 120P -- 121N -- 121P -- 122N 122P 123N 123P 124N 124P GCLK0P -- Alternate Outputs Alternate 208 PQFP 256 fpBGA 484 fpBGA Primary Macrocell/ Macrocell 1 Macrocell 2 Input Pin Number Ball Number Ball Number Function O30 O28 O26 O24 O22 VCCO0 O20 GND (Bank 0) O18 O16 O14 O12 O10 O8 O6 O4 O2 VCCO0 O0 GND (Bank 0) P30 P28 P26 VCC P24 P22 P20/CLK_OUT0 P18 P16 GND P14 VCCO0 P12 GND (Bank 0) P10 P8/PLL_RST0 P6 P4/PLL_FBK0 P2 P0 GCLK0 VCCJ O11 O10 M17 M16 M15 -- M14 -- M13 M12 O9 O8 O7 O6 O5 O4 O3 -- O2 -- O1 O0 O31 -- O30 M11 M10 M9 M8 -- M7 -- M6 -- M5 M4 -- -- -- -- -- -- P18 P16 O17 O16 O15 -- O14 -- O13 O12 P14 P12 P10 P8 P6 P4 P2 -- P0 -- -- -- -- -- -- O11 O10 O9 O8 -- O7 -- O6 -- O5 O4 -- -- -- -- -- -- O31 O29 O27 O25 O23 -- O21 -- O19 O17 O15 O13 O11 O9 O7 O5 O3 -- O1 -- P31 P29 P27 -- P25 P23 P21 P19 P17 -- P15 -- P13 -- P11 P9 P7 P5 P3 P1 -- -- 208 1 2 3 4 5 6 7 8 9 -- -- -- -- -- -- -- -- -- -- -- -- -- 10 -- 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 C4 E4 B1 C1 D3 VCCO0 C2 E3 D2 -- -- -- -- -- -- -- VCCO0 -- D1 E1 F4 VCC F5 E2 F2 F1 G1 GND F3 VCCO0 G5 H5 G4 G3 H3 G2 H1 H2 See Power Supply and NC Connections Table B4 A4 B3 A3 F5 VCCO0 G6 H6 G5 D3 D2 E4 E3 F4 G4 C2 VCCO0 C1 F3 G3 H4 VCC J4 H5 J5 E2 F2 GND D1 VCCO0 E1 J3 H2 G2 G1 H1 J1 N7 GND (Bank 0) GND (Bank 0) GND (Bank 0) GND (Bank 0) GND (Bank 0) GND (Bank 0) 56 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5512MX Logic Signal Connections (Continued) sysIO Bank -- -- -- -- -- -- 1 1 1 1 1 1 -- 1 -- 1 -- 1 1 1 1 1 -- 1 1 1 1 1 -- 1 -- 1 1 1 1 -- 1 1 1 1 -- 1 -- LVDS Pair GCLK0N -- -- -- -- -- 0P 0N 1P 1N 2P 2N -- 3P -- 3N -- 4P 4N 5P 5N 6P -- 6N 7P 7N 8P 8N -- 9P -- 9N 10P 10N -- -- 11P 11N 12P 12N -- -- -- Alternate Outputs Alternate 208 PQFP 256 fpBGA 484 fpBGA Primary Macrocell/ Macrocell 1 Macrocell 2 Input Pin Number Ball Number Ball Number Function GCLK1 GND TDI TMS TCK TDO A0/DATA0 A2/DATA1 A4/DATA2 A6/DATA3 A8/DATA4 A10/DATA5 GND (Bank 1) A12/DATA6 VCCO1 A14/DATA7 GND A16/INITB A18/CSB A20/READ A22/CCLK A24 VCC A26 A28 A30 B0 B2 GND (Bank 1) B4 VCCO1 B5 B6 B8 B10 DONE B14 B16 B18 B20 PROGRAMB B22 GND (Bank 1) -- -- -- -- -- -- B0 B1 B2 B3 B4 B5 -- B6 -- B7 -- B8 B9 B10 B11 -- -- -- -- -- A0 A2 -- A4 -- A6 A8 A10 A12 -- B12 B13 B14 B15 -- A14 -- -- -- -- -- -- -- D0 D1 D2 D3 D4 D5 -- D6 -- D7 -- D8 D9 D10 D11 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- D12 D13 D14 D15 -- -- -- -- -- -- -- -- -- A1 A3 A5 A7 A9 A11 -- A13 -- A15 -- A17 A19 A21 A23 A25 -- A27 A29 A31 B1 B3 -- -- -- -- B7 B9 B11 -- B15 B17 B19 B21 -- B23 -- 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 -- 49 -- -- -- -- -- -- -- -- -- -- -- -- 50 51 52 53 54 55 -- 56 J2 GND H6 H4 J6 K2 K3 J3 J5 J4 L2 M1 K4 VCCO1 L3 GND K5 L5 N1 M2 -- VCC P11 M3 L4 N2 P2 R1 VCCO1 R2 T2 T3 -- M4 N3 P4 N5 M6 R3 P5 P7 GND R1 R2 T1 V1 W1 Y1 P3 R3 T2 U2 V2 VCCO1 W2 GND R4 T4 R6 R5 U3 VCC V3 Y2 W3 U5 T5 U4 VCCO1 V4 AA3 AB3 Y4 AA4 AB4 AB5 T6 U7 W5 U8 GND (Bank 1) GND (Bank 1) GND (Bank 1) GND (Bank 1) GND (Bank 1) GND (Bank 1) 57 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5512MX Logic Signal Connections (Continued) sysIO Bank 1 -- 1 1 1 1 1 1 1 1 1 1 1 -- -- -- 1 1 1 1 1 1 1 1 1 1 1 -- 1 -- 1 1 1 -- 1 1 2 2 -- -- 2 2 2 LVDS Pair 13P -- 13N 14P 14N 15P 15N 16P 16N 17P 17N 18P 18N -- -- -- 19P 19N 20P 20N 21P 21N 22P 22N -- 23P 23N -- 24P -- 24N 25P 25N -- 26P 26N 27P 27N -- -- 28P 28N 29P Alternate Outputs Alternate 208 PQFP 256 fpBGA 484 fpBGA Primary Macrocell/ Macrocell 1 Macrocell 2 Input Pin Number Ball Number Ball Number Function B24 VCCO1 B26 B28 B30 C0 C2 C4 C8 C10 C12 C16 C18 GND0 (Bank 1) CFG0 VCCO1 C24 C26 C28 D0 D2 D4 D6 D8 D10/VREF1 D12 D16 GND (Bank 1) D18 VCCO1 D20 D22 D24 VCC D26 D28 E0 E2 GND GND E4 E6 E8 A16 -- A18 A20 A22 -- -- -- -- -- -- -- -- -- -- -- B16 B17 B18 B19 B20 B21 B22 B23 -- B24 B25 -- B26 -- B27 B28 B29 -- B30 B31 F0 F1 -- -- F2 F3 F4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- D16 D17 D18 D19 D20 D21 D22 D23 -- D24 D25 -- D26 -- D27 D28 D29 -- D30 D31 H0 H1 -- -- H2 H3 H4 B25 -- B27 B29 B31 C1 C3 C5 C9 C11 C13 C17 C19 -- -- -- C25 C27 C29 D1 D3 D5 D7 D9 D11 D13 D17 -- D19 -- D21 D23 D25 -- D27 D29 E1 E3 -- -- E5 E7 E9 -- 57 -- -- -- -- -- -- -- -- -- -- -- -- 58 -- 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 -- 82 83 84 T4 VCCO1 T5 R4 N6 R5 P6 -- -- -- M7 1 V6 VCCO1 V7 Y5 AA5 Y6 Y7 AA6 AA7 W7 V8 W8 U9 U10 VCCO1 AB7 AA8 AB8 AB9 W9 Y9 AB10 AA10 W10 Y10 Y11 V9 VCCO1 V10 AA11 AB11 VCC U11 V11 AB12 AA12 GND GND Y12 AA13 V12 T6 R6 L8 VCCO1 T7 R7 N7 P7 T8 R8 M8 P8 L9 N8 M9 N10 VCCO1 T9 T10 R9 VCC P9 N9 T11 T12 NC GND P10 R10 R11 GND (Bank 1) GND (Bank 1) GND (Bank 1) GND (Bank 1) 58 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5512MX Logic Signal Connections (Continued) sysIO Bank -- 2 -- 2 2 2 2 2 2 2 2 2 2 2 -- 2 -- 2 2 2 2 2 2 2 2 2 2 2 -- 2 -- 2 2 2 2 2 2 2 2 2 2 2 -- LVDS Pair -- 29N -- 30P 30N 31P 31N 32P 32N 33P 33N 34P 34N 35P -- 35N -- 36P 36N 37P 37N 38P 38N 39P 39N 40P 40N 41P -- 41N -- 42P 42N 43P 43N 44P 44N 45P 45N 46P 46N 47P -- Alternate Outputs Alternate 208 PQFP 256 fpBGA 484 fpBGA Primary Macrocell/ Macrocell 1 Macrocell 2 Input Pin Number Ball Number Ball Number Function VCCO2 E10 GND (Bank 2) E12 E16 E18 E20/VREF2 E22 E24 E26 E28 F0 F2 F4 VCCO2 F6 GND (Bank 2) F8 F10 F12 F16 F18 F20 F22 F24 F26 F28 G0 VCCO2 G2 GND (Bank 2) G4 G6 G8 G10 G12 G14 G16 G18 G20 G22 G24 VCCO2 -- F5 -- F6 F7 -- -- F8 F9 F10 F11 F12 F13 F14 -- F15 -- E0 E2 E4 E6 E8 E10 E12 E16 E20 E22 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- H5 -- H6 H7 -- -- H8 H9 H10 H11 H12 H13 H14 -- H15 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- E11 -- E13 E17 E19 E21 E23 E25 E27 E29 F1 F3 F5 -- F7 -- F9 F11 F13 F17 F19 F21 F23 F25 F27 F29 G1 -- G3 -- G5 G7 G9 G11 G13 G15 G17 G19 G21 G23 G25 -- 85 86 87 88 89 90 91 92 93 94 95 96 97 98 -- 99 -- -- -- -- -- -- -- -- -- -- -- -- 100 -- 101 102 103 -- -- -- -- -- -- 104 105 106 107 VCCO2 M10 M11 T13 P11 T14 R12 R13 N11 T15 R14 N12 P12 VCCO2 R15 -- -- -- -- -- -- -- -- -- -- -- VCCO2 -- P13 P15 M13 P14 -- -- -- -- R16 P16 N15 VCCO2 VCCO2 U12 AB13 Y13 V13 W13 V14 W14 Y14 AB14 AB15 AA15 U13 VCCO2 U14 W15 W16 Y16 AA16 AB16 AA17 Y17 AA18 W17 W18 V15 VCCO2 U15 Y18 V17 V16 U16 AB18 AB19 U18 T17 AB20 AA20 Y19 VCCO2 GND (Bank 2) GND (Bank 2) GND (Bank 2) GND (Bank 2) GND (Bank 2) GND (Bank 2) 59 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5512MX Logic Signal Connections (Continued) sysIO Bank 2 -- 2 2 2 2 2 -- 2 2 2 2 2 -- 2 -- 2 -- 2 2 2 2 2 2 -- -- -- -- -- -- -- -- 3 3 3 3 3 3 -- 3 -- 3 -- LVDS Pair 47N -- 48P 48N 49P 49N 50P -- 50N 51P 51N 52P 52N -- 53P -- 53N -- 54P 54N 55P 55N 56P 56N -- -- -- -- -- GCLK3N -- GCLK3P 57N 57P 58N 58P 59N 59P -- 60N -- 60P -- Alternate Outputs Alternate 208 PQFP 256 fpBGA 484 fpBGA Primary Macrocell/ Macrocell 1 Macrocell 2 Input Pin Number Ball Number Ball Number Function G26 GND (Bank 2) G28 G30 H0 H2 H4 VCC H6 H8 H10 H12 H14 GND H16 VCCO2 H18 GND (Bank 2) H20 H22 H24 H26 H28 H30 TOE RESET GOE0 GOE1 GNDP GCLK2 VCCP GCLK3 I30 I28 I26 I24/PLL_FBK1 I22/PLL_RST1 I20 GND (Bank 3) I18 VCCO3 I16 GND -- -- F16 F17 F18 F19 E24 -- E26 F20 F21 F22 F23 -- F24 -- F25 -- F26 F27 F28 F29 F30 F31 -- -- -- -- -- -- -- -- -- -- -- -- I27 I26 -- I25 -- I24 -- -- -- H16 H17 H18 H19 -- -- -- H20 H21 H22 H23 -- H24 -- H25 -- H26 H27 H28 H29 H30 H31 -- -- -- -- -- -- -- -- -- -- -- -- K27 K26 -- K25 -- K24 -- G27 -- G29 G31 H1 H3 H5 -- H7 H9 H11 H13 H15 -- H17 -- H19 -- H21 H23 H25 H27 H29 H31 -- -- -- -- -- -- -- -- I31 I29 I27 I25 I23 I21 -- I19 -- I17 -- 108 109 110 111 112 113 -- 114 -- 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 135 137 138 139 140 141 142 143 144 145 146 147 148 N14 N16 M16 M14 M15 -- VCC NC L13 L12 L15 L16 GND L14 VCCO2 K15 K14 K12 K13 J13 J14 J12 J15 J11 H11 H13 H15 H16 H14 G16 G15 F15 H12 G14 F16 VCCO3 E16 GND V19 T18 R17 U19 T19 V20 VCC U20 W20 Y21 R18 R19 GND W21 VCCO2 Y22 R20 P20 T21 R21 U21 V21 W22 V22 T22 R22 P16 N16 J22 H22 E22 E21 G22 F21 H21 VCCO3 G21 GND GND (Bank 2) GND (Bank 2) GND (Bank 2) GND (Bank 2) See Power Supply and NC Connections Table See Power Supply and NC Connections Table GND (Bank 3) GND (Bank 3) 60 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5512MX Logic Signal Connections (Continued) sysIO Bank 3 3 3 3 3 -- 3 3 3 -- 3 -- 3 3 3 3 3 3 3 3 3 -- 3 -- 3 3 3 3 3 3 3 3 3 3 3 -- 3 -- 3 3 3 3 3 LVDS Pair 61N 61P 62N 62P 63N -- 63P 64N 64P -- 65N -- 65P 66N 66P 67N 67P 68N 68P 69N 69P -- 70N -- 70P 71N 71P 72N 72P 73N 73P 74N 74P 75N 75P -- 76N -- 76P 77N 77P 78N 78P Alternate Outputs Alternate 208 PQFP 256 fpBGA 484 fpBGA Primary Macrocell/ Macrocell 1 Macrocell 2 Input Pin Number Ball Number Ball Number Function I14 I12 I10 I8/CLK_OUT1 I6 VCC I4 I2 I0 GND (Bank 3) J30 VCCO3 J28 J26 J24 J22 J20 J18 J16 J14 J12 GND (Bank 3) J10 VCCO3 J8 J6 J4 J2 J0 K30 K28 K26 K24 K22 K21 GND (Bank 3) K20 VCCO3 K18 K16 K14 K12 K10 I23 I22 I21 I20 K31 -- K30 K29 K28 -- K27 -- K26 K25 K24 K23 K22 K21 K20 K19 K18 -- K17 -- K16 K15 K14 K13 K12 I19 I18 I17 I16 I31 I30 -- K11 -- K10 K9 K8 K7 K6 K23 K22 K21 K20 -- -- L30 L28 L26 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- K19 K18 K17 K16 K31 K30 -- L21 -- L20 L18 L16 L12 L10 I15 I13 I11 I9 I7 -- I5 I3 I1 -- J31 -- J29 J27 J25 J23 J21 J19 J17 J15 J13 -- J11 -- J9 J7 J5 J3 J1 K31 K29 K27 K25 K23 -- -- -- -- K19 K17 K15 K13 K11 149 150 151 152 -- 153 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 154 155 156 157 158 159 160 -- 161 -- -- -- -- -- G13 G12 F14 E15 F12 VCC F13 D16 D15 -- VCCO3 -- -- -- -- -- -- -- C16 B16 C15 VCCO3 B15 E14 D14 E13 A15 D12 B14 C13 A14 A13 B13 D11 VCCO3 B12 C12 E11 -- -- D22 D21 J20 J19 E20 VCC F20 H17 H18 J18 VCCO3 H19 G20 G19 C22 C21 D20 C19 F19 E19 G18 VCCO3 F18 B20 B19 A20 A19 D18 C18 G17 F16 E17 D17 B18 VCCO3 A18 C17 B17 C16 B16 GND (Bank 3) GND (Bank 3) GND (Bank 3) GND (Bank 3) GND (Bank 3) GND (Bank 3) 61 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5512MX Logic Signal Connections (Continued) sysIO Bank 3 3 3 3 3 3 -- 3 -- 3 3 3 3 3 3 3 3 3 3 3 -- 3 -- 3 3 3 -- 3 3 0 0 -- -- 0 0 0 -- 0 -- 0 0 0 0 LVDS Pair 79N 79P 80N 80P 81N 81P -- 82N -- 82P 83N 83P 84N 84P 85N 85P 86N 86P 87N 87P -- 88N -- 88P 89N 89P -- 90N 90P 91N 91P -- -- 92N 92P 93N -- 93P -- 94N 94P 95N 95P Alternate Outputs Alternate 208 PQFP 256 fpBGA 484 fpBGA Primary Macrocell/ Macrocell 1 Macrocell 2 Input Pin Number Ball Number Ball Number Function K8 K6 K5 K4 K2 K0 GND (Bank 3) L30 VCCO3 L28 L26 L24 L22 L21 L20 L18 L16/VREF3 L14 L12 L10 GND (Bank 3) L8 VCCO3 L6 L5 L4 VCC L2 L0 M30 M28 GND GND M26 M24 M22 VCCO0 M21 GND (Bank 0) M20 M18 M16/VREF0 M14 K5 K4 K3 K2 K1 K0 -- I15 -- I14 I13 I12 I11 I10 I9 I8 I29 I28 I7 I6 -- I5 -- I4 I3 I2 -- I1 I0 M31 M30 -- -- M29 M28 M27 -- M26 -- M25 M24 M3 M2 L8 L6 L5 L4 L2 L0 -- K15 -- K14 K13 K12 K11 K10 K9 K8 K29 K28 K7 K6 -- K5 -- K4 K3 K2 -- K1 K0 O31 O30 -- -- O29 O28 O27 -- O26 -- O25 O24 O3 O2 K9 K7 -- -- K3 K1 -- L31 -- L29 L27 L25 L23 -- -- L19 L17 L15 L13 L11 -- L9 -- L7 -- -- -- L3 L1 M31 M29 -- -- M27 M25 M23 -- M22 -- M21 M19 M17 M15 -- -- -- -- -- -- -- 162 -- 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 -- 186 187 188 189 190 191 192 193 194 195 -- -- -- E101 A12 A11 B11 VCCO3 C11 B10 A10 C10 D10 C9 E9 D9 F9 A9 F8 E8 VCCO3 A8 B9 D8 VCC B8 C8 B7 A7 -- GND D7 C7 B6 VCCO0 E7 E6 A6 A5 A4 F13 F15 D16 E16 A16 A15 B15 VCCO3 A14 D15 E15 D14 F14 A13 B13 C14 E14 E13 F12 D13 VCCO3 C13 E12 C12 VCC B12 A12 E11 C11 GND GND B11 A11 F11 VCCO0 F10 E10 C10 D10 B10 GND (Bank 3) GND (Bank 3) GND (Bank 3) GND (Bank 3) GND (Bank 0) GND (Bank 0) 62 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5512MX Logic Signal Connections (Continued) sysIO Bank 0 0 0 0 0 0 0 -- 0 -- 0 0 0 0 0 0 0 0 0 0 0 -- 0 -- 0 0 0 0 0 0 LVDS Pair 96N 96P 97N 97P 98N 98P 99N -- 99P -- 100N 100P 101N 101P 102N 102P 103N 103P 104N 104P 105N -- 105P -- 106N 106P 107N 107P 108N 108P Alternate Outputs Alternate 208 PQFP 256 fpBGA 484 fpBGA Primary Macrocell/ Macrocell 1 Macrocell 2 Input Pin Number Ball Number Ball Number Function M12 M10 M8 M6 M5 M4 M2 VCCO0 M0 GND (Bank 0) N30 N28 N26 N24 N22 N21 N20 N18 N16 N14 N12 VCCO0 N10 GND (Bank 0) N8 N6 N5 N4 N2 N0 M23 M22 M21 M20 M19 M18 M1 -- M0 -- O29 O28 O27 O26 O25 O24 O23 O22 O21 O20 O19 -- O18 -- O17 O16 O15 O14 O13 O12 O23 O22 O21 O20 O19 O18 O1 -- O0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- M13 M11 M9 M7 -- -- M3 -- M1 -- N31 N29 N27 N25 N23 -- -- N19 N17 N15 N13 -- N11 -- N9 N7 -- -- N3 N1 196 197 198 199 200 201 202 -- 203 -- -- -- -- -- -- -- -- -- -- -- -- 204 -- 205 -- -- 206 207 -- -- B5 A3 B4 B3 C5 C6 D5 VCCO0 D6 -- -- -- -- -- -- -- -- -- -- -- VCCO0 -- -- -- A2 B2 -- -- A10 A9 C9 D9 F9 E9 A8 VCCO0 B8 A7 B7 A5 B5 B6 C7 E8 E7 E6 D6 D8 VCCO0 F8 F7 D7 C6 C5 C4 D5 GND (Bank 0) GND (Bank 0) GND (Bank 0) GND (Bank 0) 1. Not available for differential pair. Global Clock LVDS pair options: GCLK0 and GCLK1, as well as GCLK2 and GCLK3, can be paired together to receive differential clocks; where GCLK0 and GCLK3 are the positive LVDS inputs. 63 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5768MX Logic Signal Connections Primary Macrocell/ sysIO Bank LVDS Pair Function 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 127N 127P 128N 128P 129N 129P 130N 130P 131N 131P 132N 132P 133N 133P 134N 134P 135N 135P 136N 136P 137N 137P 138N 138P 139N 139P 140N 140P 141N 141P 142N 142P S22 S20 S18 S16 S14 VCCO0 S12 GND (Bank 0) S10 S8 S6 S4 S2 VCC S0 GND T30 T28 T26 VCCO0 T24 GND (Bank 0) T22 T20 T18 VCC T16 T14 T12/CLK_OUT0 T10 T8 GND T6 VCCO0 T4 GND (Bank 0) T2 T0/PLL_RST0 U30 U28/PLL_FBK0 U26 U24 Alternate Outputs Macrocell 1 S11 S10 Q17 Q16 Q15 Q14 Q13 Q12 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 S31 S30 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 U31 U30 U29 U28 Macrocell 2 T18 T16 S17 S16 S15 S14 S13 S12 T14 T12 T10 T8 T6 T4 T2 T0 S11 S10 S9 S8 S7 S6 S5 S4 W31 W30 W29 W28 Alternate Inputs S23 S21 S19 S17 S15 S13 S11 S9 S7 S5 S3 S1 T31 T29 T27 T25 T23 T21 T19 T17 T15 T13 T11 T9 T7 T5 T3 T1 U31 U29 U27 U25 256 fpBGA Ball Number C4 E4 B1 C1 D3 VCCO0 C2 E3 D2 -- -- -- VCC -- GND -- -- -- VCCO0 -- D1 E1 F4 VCC F5 E2 F2 F1 G1 GND F3 VCCO0 G5 H5 G4 G3 H3 -- -- 484 fpBGA Ball Number B4 A4 B3 A3 F5 VCCO0 G6 H6 G5 D3 D2 E4 VCC E3 GND F4 G4 C2 VCCO0 C1 F3 G3 H4 VCC J4 H5 J5 E2 F2 GND D1 VCCO0 E1 J3 H2 G2 G1 J6 K4 GND (Bank 0) GND (Bank 0) GND (Bank 0) GND (Bank 0) GND (Bank 0) GND (Bank 0) 64 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5768MX Logic Signal Connections (Continued) Primary Macrocell/ sysIO Bank LVDS Pair Function 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143N 143P 144N 144P 145N 145P 146N 146P 147N 147P 148N 148P 149N 149P 150N 150P 151N 151P 152N 152P 153N 153P 154N 154P 155N 155P 156N 156P GCLK0P GCLK0N U22 VCCO0 U20 GND (Bank 0) U18 U16 U14 U12 U10 U8 U6 U4 U2 VCCO0 U0 GND (Bank 0) W30 W28 W26 VCC W24 W22 W20 W18 W16 GND W14 VCCO0 W12 GND (Bank 0) W10 W8 W6 W4 W2 W0 GCLK0 VCCJ GCLK1 GND TDI TMS Alternate Outputs Macrocell 1 U27 U26 U25 U24 U23 U22 U21 U20 U19 U18 U17 U16 U15 U14 U13 U12 U11 U10 U9 U8 U7 U6 U5 U4 U3 U2 U1 U0 Macrocell 2 W27 W26 W25 W24 W23 W22 W21 W20 W19 W18 W17 W16 W15 W14 W13 W12 W11 W10 W9 W8 W7 W6 W5 W4 W3 W2 W1 W0 Alternate Inputs U23 U21 U19 U17 U15 U13 U11 U9 U7 U5 U3 U1 W31 W29 W27 W25 W23 W21 W19 W17 W15 W13 W11 W7 W5 W3 W1 256 fpBGA Ball Number -- VCCO0 -- -- -- -- -- -- -- -- -- -- VCCO0 -- -- -- -- VCC -- -- -- -- -- GND -- VCCO0 -- -- -- -- -- G2 H1 H2 484 fpBGA Ball Number K6 VCCO0 K3 K5 K2 L5 K1 L6 L1 M5 L2 N5 VCCO0 L3 M6 M2 P5 VCC P6 M3 N6 N2 P1 GND N3 VCCO0 M8 N8 P2 P8 N4 H1 J1 N7 GND (Bank 0) GND (Bank 0) GND (Bank 0) GND (Bank 0) GND (Bank 0) GND (Bank 0) See Power Supply and NC Connections Table J2 GND H6 H4 P7 GND R1 R2 65 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5768MX Logic Signal Connections (Continued) Primary Macrocell/ sysIO Bank LVDS Pair Function 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0P 0N 1P 1N 2P 2N 3P 3N 4P 4N 5P 5N 6P 6N 7P 7N 8P 8N 9P 9N 10P 10N 11P 11N 12P 12N 13P 13N 14P 14N TCK TDO A30/DATA0 A28/DATA1 A26/DATA2 A24/DATA3 A22/DATA4 A20/DATA5 GND (Bank 1) A18/DATA6 VCCO1 A16/DATA7 GND A14/INITB A12/CSB A10/READ A8/CCLK A6 VCC A4 A2 A0 B30 B28 GND (Bank 1) B26 VCCO1 B24 B22 B20 B18 DONE B14 B12 GND (Bank 1) B10 VCCO1 B8 B6 B4 B2 B0 PROGRAMB Alternate Outputs Macrocell 1 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 D0 D2 D4 D6 D8 D10 D12 C12 C13 C14 C15 Macrocell 2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 Alternate Inputs A31 A29 A27 A25 A23 A21 A19 A17 A15 A13 A11 A9 A7 A5 A3 A1 B31 B29 B27 B25 B23 B21 B19 B15 B13 B11 B9 B7 B5 B3 B1 256 fpBGA Ball Number J6 K2 K3 J3 J5 J4 L2 M1 K4 VCCO1 L3 GND K5 L5 N1 M2 -- VCC P1 M3 L4 N2 P2 R1 VCCO1 R2 T2 T3 -- M4 -- -- -- VCCO1 -- N3 P4 N5 M6 R3 484 fpBGA Ball Number T1 V1 W1 Y1 P3 R3 T2 U2 V2 VCCO1 W2 GND R4 T4 R6 R5 U3 VCC V3 Y2 W3 U5 T5 U4 VCCO1 V4 AA3 AB3 Y4 AA4 AB2 U6 V5 VCCO1 W6 AB4 AB5 T6 U7 W5 GND (Bank 1) GND (Bank 1) GND (Bank 1) GND (Bank 1) GND (Bank 1) GND (Bank 1) 66 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5768MX Logic Signal Connections (Continued) Primary Macrocell/ sysIO Bank LVDS Pair Function 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 15P 15N 16P 16N 17P 17N 18P 18N 19P 19N 20P 20N 21P 21N 22P 22N 23P 23N 24P 24N 25P 25N 26P 26N 27P 27N 28P 28N 29P C28 GND (Bank 1) C26 VCCO1 C24 GND C22 VCC C20 C18 C16 C14 C12 C10 C8 C6 C4 GND (Bank 1) CFG0 VCCO1 C0 D30 D28 D26 D24 D22 D20 D18 D16/VREF1 D14 D12 GND (Bank 1) D10 VCCO1 D8 D6 GND D4 VCC D2 D0 E0 VCC Alternate Outputs Macrocell 1 D14 D16 D18 D20 D22 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 F0 Macrocell 2 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 H0 Alternate Inputs C29 C27 C25 C23 C21 C19 C17 C15 C13 C11 C9 C7 C5 C1 D31 D29 D27 D25 D23 D21 D19 D17 D15 D13 D11 D9 D7 D5 D3 D1 E1 256 fpBGA Ball Number P5 T4 VCCO1 T5 GND R4 VCC N6 R5 P6 -- -- -- M7 T6 R6 L8 VCCO1 T7 R7 N7 P7 T8 R8 M8 P8 L9 N8 M9 N10 VCCO1 T9 T10 GND R9 VCC P9 N9 T11 VCC 484 fpBGA Ball Number U8 V6 VCCO1 V7 GND Y5 VCC AA5 Y6 Y7 AA6 AA7 W7 V8 W8 U9 U10 VCCO1 AB7 AA8 AB8 AB9 W9 Y9 AB10 AA10 W10 Y10 Y11 V9 VCCO1 V10 AA11 GND AB11 VCC U11 V11 AB12 VCC GND (Bank 1) GND (Bank 1) GND (Bank 1) GND (Bank 1) GND (Bank 1) GND (Bank 1) 67 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5768MX Logic Signal Connections (Continued) Primary Macrocell/ sysIO Bank LVDS Pair Function 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 29N 30P 30N 31P 31N 32P 32N 33P 33N 34P 34N 35P 35N 36P 36N 37P 37N 38P 38N 39P 39N 40P 40N 41P 41N 42P 42N 43P 43N 44P 44N 45P 45N 46P E2 GND E4 E6 E8 VCCO2 E10 GND (Bank 2) E12 E14 E16 E18/VREF2 E20 E22 E24 E26 E28 E30 F0 VCCO2 F2 GND (Bank 2) F4 F6 F8 F10 F12 F14 F16 F18 F20 VCC F22 GND F24 VCCO2 F26 GND (Bank 2) F28 F30 G0 G2 G4 Alternate Outputs Macrocell 1 F1 F2 F3 F4 F5 F6 F7 H0 H1 F8 F9 F10 F11 F12 F13 F14 F15 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 Macrocell 2 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 E0 E2 E4 E6 E8 E10 E12 E16 E20 E22 Alternate Inputs E3 E5 E7 E9 E11 E13 E15 E17 E19 E21 E23 E25 E27 E29 E31 F1 F3 F5 F7 F9 F11 F13 F15 F17 F19 F21 F23 F25 F27 F29 F31 G1 G3 G5 256 fpBGA Ball Number T12 GND P10 R10 R11 VCCO2 M10 M11 T13 P11 T14 R12 R13 N11 T15 R14 N12 P12 VCCO2 R15 -- -- -- -- -- -- -- -- -- VCC -- GND -- VCCO2 -- P13 P15 M13 P14 -- 484 fpBGA Ball Number AA12 GND Y12 AA13 V12 VCCO2 U12 AB13 Y13 V13 W13 V14 W14 Y14 AB14 AB15 AA15 U13 VCCO2 U14 W15 W16 Y16 AA16 AB16 AA17 Y17 AA18 W17 VCC W18 GND V15 VCCO2 U15 Y18 V17 V16 U16 AB18 GND (Bank 2) GND (Bank 2) GND (Bank 2) GND (Bank 2) GND (Bank 2) GND (Bank 2) 68 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5768MX Logic Signal Connections (Continued) Primary Macrocell/ sysIO Bank LVDS Pair Function 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 46N 47P 47N 48P 48N 49P 49N 50P 50N 51P 51N 52P 52N 53P 53N 54P 54N 55P 55N 56P 56N 57P 57N 58P 58N 59P 59N 60P 60N G6 G8 VCCO2 G10 GND (Bank 2) G12 G14 G16 G18 G20 G22 G24 VCCO2 G26 GND (Bank 2) G28 G30 H0 H2 H4 VCC H6 H8 H10 H12 H14 GND H16 VCCO2 H18 GND (Bank 2) H20 H22 H24 H26 H28 H30 TOE RESETB GOE0 GOE1 GNDP Alternate Outputs Macrocell 1 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 F16 F17 F18 F19 H30 H31 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 Macrocell 2 H16 H17 H18 H19 E24 E26 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 Alternate Inputs G7 G9 G11 G13 G15 G17 G19 G21 G23 G25 G27 G29 G31 H1 H3 H5 H7 H9 H11 H13 H15 H17 H19 H21 H23 H25 H27 H29 H31 256 fpBGA Ball Number -- -- VCCO2 -- -- -- -- -- R16 P16 N15 VCCO2 N14 N16 M16 M14 M15 -- VCC -- L13 L12 L15 L16 GND L14 VCCO2 K15 K14 K12 K13 J13 J14 J12 J15 J11 H11 H13 484 fpBGA Ball Number AB19 AA19 VCCO2 U17 V18 AB21 U18 T17 AB20 AA20 Y19 VCCO2 V19 T18 R17 U19 T19 V20 VCC U20 W20 Y21 R18 R19 GND W21 VCCO2 Y22 R20 P20 T21 R21 U21 V21 W22 V22 T22 R22 GND (Bank 2) GND (Bank 2) GND (Bank 2) GND (Bank 2) GND (Bank 2) GND (Bank 2) See Power Supply and NC Connections Table 69 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5768MX Logic Signal Connections (Continued) Primary Macrocell/ sysIO Bank LVDS Pair Function 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 GCLK3N GCLK3P 61N 61P 62N 62P 63N 63P 64N 64P 65N 65P 66N 66P 67N 67P 68N 68P 69N 69P 70N 70P 71N 71P 72N 72P 73N 73P 74N 74P 75N 75P 76N GCLK2 VCCP GCLK3 J0 J2 J4 J6 J8 J10 GND (Bank 3) J12 VCCO3 J14 GND J16 J18 J20 J22 J24 VCC J26 J28 J30 GND (Bank 3) L0 VCCO3 L2 L4 L6 L8 L10 L12 L14 L16 L18 GND (Bank 3) L20 VCCO3 L22 L24 L26 L28 Alternate Outputs Macrocell 1 L31 L30 L29 L28 L27 L26 L25 L24 L23 L22 L21 L20 L19 L18 L17 L16 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 Macrocell 2 J31 J30 J29 J28 J27 J26 J25 J24 J23 J22 J21 J20 J19 J18 J17 J16 J15 J14 J13 J12 J11 J10 J9 J8 J7 J6 J5 J4 J3 J2 J1 Alternate Inputs J3 J5 J7 J9 J11 J13 J15 J17 J19 J21 J23 J25 J27 J29 J31 L3 L5 L7 L9 L11 L13 L15 L17 L19 L21 L23 L25 L27 L29 256 fpBGA Ball Number H15 484 fpBGA Ball Number P16 See Power Supply and NC Connections Table H16 H14 G16 -- -- -- -- -- VCCO3 -- GND -- -- -- -- -- VCC -- -- -- -- VCCO3 -- -- -- -- -- -- -- -- -- -- VCCO3 -- -- -- G15 N16 J22 H22 N19 P15 P21 N15 M15 VCCO3 N20 GND P22 N21 N17 M20 P17 VCC P18 M21 M17 L20 VCCO3 N18 L21 M18 L22 L17 K22 L18 K21 K18 K20 VCCO3 K17 K19 J17 E22 GND (Bank 3) GND (Bank 3) GND (Bank 3) GND (Bank 3) GND (Bank 3) GND (Bank 3) 70 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5768MX Logic Signal Connections (Continued) Primary Macrocell/ sysIO Bank LVDS Pair Function 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 76P 77N 77P 78N 78P 79N 79P 80N 80P 81N 81P 82N 82P 83N 83P 84N 84P 85N 85P 86N 86P 87N 87P 88N 88P 89N 89P 90N 90P 91N 91P 92N 92P L30/PLL_FBK1 M0/PLL_RST1 M2 GND (Bank 3) M4 VCCO3 M6 GND M8 M10 M12 M14/CLK_OUT1 M16 VCC M18 M20 M22 GND (Bank 3) M24 VCCO3 M26 M28 M30 GND N0 VCC N2 N4 N6 N8 N10 GND (Bank 3) N12 VCCO3 N14 N16 N18 N20 N22 N24 N26 N28 N30 Alternate Outputs Macrocell 1 L0 P27 P26 P25 P24 P23 P22 P21 P20 N31 N30 N29 N28 N27 N26 N25 N24 N23 N22 N21 N20 N19 N18 N17 N16 N15 N14 N13 N12 P19 P18 P17 P16 Macrocell 2 J0 N27 N26 N25 N24 N23 N22 N21 N20 M30 M28 M26 N19 N18 N17 N16 Alternate Inputs L31 M1 M3 M5 M9 M11 M13 M15 M17 M19 M21 M23 M25 M27 M29 M31 N1 N3 N9 N11 N13 N15 N17 N19 N21 N23 N25 N27 N29 N31 256 fpBGA Ball Number F15 H12 G14 F16 VCCO3 E16 GND G13 G12 F14 E15 F12 VCC F13 D16 D15 -- VCCO3 -- -- -- GND -- VCC -- -- -- C16 B16 C15 VCCO3 B15 E14 D14 E13 A15 D12 B14 C13 A14 484 fpBGA Ball Number E21 G22 F21 H21 VCCO3 G21 GND D22 D21 J20 J19 E20 VCC F20 H17 H18 J18 VCCO3 H19 G20 G19 GND C22 VCC C21 D20 C19 F19 E19 G18 VCCO3 F18 B20 B19 A20 A19 D18 C18 G17 F16 GND (Bank 3) GND (Bank 3) GND (Bank 3) GND (Bank 3) GND (Bank 3) GND (Bank 3) 71 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5768MX Logic Signal Connections (Continued) Primary Macrocell/ sysIO Bank LVDS Pair Function 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 0 93N 93P 94N 94P 95N 95P 96N 96P 97N 97P 98N 98P 99N 99P 100N 100P 101N 101P 102N 102P 103N 103P 104N 104P 105N 105P 106N 106P 107N 107P 108N 108P 109N O0 O2 GND (Bank 3) O4 VCCO3 O6 GND O8 VCC O10 O12 O14 O16 O18 O20 O22 O24 O26 GND (Bank 3) O28 VCCO3 O30 P0 P2 P4 P6 P8 P10 P12/VREF3 P14 P16 P18 GND (Bank 3) P20 VCCO3 P22 P24 GND P26 VCC P28 P30 Q30 Alternate Outputs Macrocell 1 P31 P30 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 P15 P14 P13 P12 P11 P10 P9 P8 P29 P28 P7 P6 P5 P4 P3 P2 P1 P0 Q31 Macrocell 2 N31 N30 M21 M20 M18 M16 M12 M10 M8 M6 M5 M4 M2 M0 N15 N14 N13 N12 N11 N10 N9 N8 N29 N28 N7 N6 N5 N4 N3 N2 N1 N0 S31 Alternate Inputs O1 O3 O5 O7 O9 O11 O13 O15 O17 O19 O21 O23 O25 O27 O29 O31 P1 P3 P5 P7 P9 P11 P13 P15 P17 P19 P21 P23 P25 P27 P29 P31 Q31 256 fpBGA Ball Number A13 B13 D11 VCCO3 B12 GND C12 VCC E11 -- -- -- -- -- E10 A12 A11 B11 VCCO3 C11 B10 A10 C10 D10 C9 E9 D9 F9 A9 F8 E8 VCCO3 A8 B9 GND D8 VCC B8 C8 B7 484 fpBGA Ball Number E17 D17 B18 VCCO3 A18 GND C17 VCC B17 C16 B16 F13 F15 D16 E16 A16 A15 B15 VCCO3 A14 D15 E15 D14 F14 A13 B13 C14 E14 E13 F12 D13 VCCO3 C13 E12 GND C12 VCC B12 A12 E11 GND (Bank 3) GND (Bank 3) GND (Bank 3) GND (Bank 3) GND (Bank 3) GND (Bank 3) 72 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5768MX Logic Signal Connections (Continued) Primary Macrocell/ sysIO Bank LVDS Pair Function 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 109P 110N 110P 111N 111P 112N 112P 113N 113P 114N 114P 115N 115P 116N 116P 117N 117P 118N 118P 119N 119P 120N 120P 121N 121P 122N 122P 123N 123P 124N 124P 125N 125P VCC Q28 GND Q26 Q24 Q22 VCCO0 Q20 GND (Bank 0) Q18 Q16 Q14/VREF0 Q12 Q10 Q8 Q6 Q4 Q2 Q0 R30 VCCO0 R28 GND (Bank 0) R26 R24 R22 R20 R18 R16 R14 R12 R10 VCC R8 GND R6 VCCO0 R4 GND (Bank 0) R2 R0 S30 S28 Alternate Outputs Macrocell 1 Q30 Q29 Q28 Q27 Q26 Q25 Q24 Q3 Q2 Q23 Q22 Q21 Q20 Q19 Q18 Q1 Q0 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 Macrocell 2 S30 S29 S28 S27 S26 S25 S24 S3 S2 S23 S22 S21 S20 S19 S18 S1 S0 Alternate Inputs Q29 Q27 Q25 Q23 Q21 Q19 Q17 Q15 Q13 Q11 Q9 Q7 Q5 Q3 Q1 R31 R29 R27 R25 R23 R21 R19 R17 R15 R13 R11 R9 R7 R5 R3 R1 S31 S29 256 fpBGA Ball Number VCC A7 GND D7 C7 B6 VCCO0 E7 E6 A6 A5 A4 B5 A3 B4 B3 C5 C6 D5 VCCO0 D6 -- -- -- -- -- -- -- -- -- VCC -- GND -- VCCO0 -- -- -- A2 B2 484 fpBGA Ball Number VCC C11 GND B11 A11 F11 VCCO0 F10 E10 C10 D10 B10 A10 A9 C9 D9 F9 E9 A8 VCCO0 B8 A7 B7 A5 B5 B6 C7 E8 E7 E6 VCC D6 GND D8 VCCO0 F8 F7 D7 C6 C5 GND (Bank 0) GND (Bank 0) GND (Bank 0) GND (Bank 0) GND (Bank 0) GND (Bank 0) 73 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5768MX Logic Signal Connections (Continued) Primary Macrocell/ sysIO Bank LVDS Pair Function 0 0 126N 126P S26 S24 Alternate Outputs Macrocell 1 S13 S12 Macrocell 2 Alternate Inputs S27 S25 256 fpBGA Ball Number -- -- 484 fpBGA Ball Number C4 D5 Global Clock LVDS pair options: GCLK0 and GCLK1, as well as GCLK2 and GCLK3, can be paired together to receive differencial clocks; where GCLK0 and GCLK3 are the positive LVDS inputs. 74 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 51024MX Logic Signal Connections sysIO Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVDS Pair 159N 159P 160N 160P 161N 161P 162N 162P 163N 163P 164N 164P 165N 165P 166N 166P 167N 167P 168N 168P 169N 169P 170N 170P 171N 171P 172N 172P 173N 173P 174N 174P Primary Macrocell/Function AA22 AA20 AA18 AA16 AA14 VCCO0 AA12 GND (Bank 0) AA10 AA8 AA6 AA4 AA2 VCC AA0 GND AB30 AB28 AB26 VCCO0 AB24 GND (Bank 0) AB22 AB20 AB18 VCC AB16 AB14 AB12/CLK_OUT0 AB10 AB8 GND AB6 VCCO0 AB4 GND (Bank 0) AB2 AB0/PLL_RST0 AC30 AC28/PLL_FBK0 AC26 AC24 Alternate Outputs Macrocell 1 AA11 AA10 Y17 Y16 Y15 Y14 Y13 Y12 AA9 AA8 AA7 AA6 AA5 AA4 AA3 AA2 AA1 AA0 AA31 AA30 Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4 AC31 AC30 AC29 AC28 Macrocell 2 AB18 AB16 AA17 AA16 AA15 AA14 AA13 AA12 AB14 AB12 AB10 AB8 AB6 AB4 AB2 AB0 AA11 AA10 AA9 AA8 AA7 AA6 AA5 AA4 AE31 AE30 AE29 AE28 AB17 AB15 AB13 AB11 AB9 AB7 AB5 AB3 AB1 AC31 AC29 AC27 AC25 Alternate Input AA23 AA21 AA19 AA17 AA15 AA13 AA11 AA9 AA7 AA5 AA3 AA1 AB31 AB29 AB27 AB25 AB23 AB21 AB19 484 fpBGA Ball Number B4 A4 B3 A3 F5 VCCO0 G6 H6 G5 D3 D2 E4 VCC E3 GND F4 G4 C2 VCCO0 C1 F3 G3 H4 VCC J4 H5 J5 E2 F2 GND D1 VCCO0 E1 J3 H2 G2 G1 J6 K4 672 fpBGA Ball Number C2 C1 D4 D3 D2 VCCO0 D1 E5 E4 E3 E2 E1 VCC F2 GND F5 G6 F4 VCCO0 F3 F1 G1 G5 VCC G4 H7 J7 G3 G2 GND H6 VCCO0 J6 H5 H4 H3 H2 H1 J1 GND (Bank 0) GND (Bank 0) GND (Bank 0) GND (Bank 0) GND (Bank 0) GND (Bank 0) 75 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 51024MX Logic Signal Connections (Continued) sysIO Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVDS Pair 175N 175P 176N 176P 177N 177P 178N 178P 179N 179P 180N 180P 181N 181P 182N 182P 183N 183P 184N 184P 185N 185P 186N 186P 187N 187P 188N 188P GCLK0P GCLK0N Primary Macrocell/Function AC22 VCCO0 AC20 GND (Bank 0) AC18 AC16 AC14 AC12 AC10 AC8 AC6 AC4 AC2 VCCO0 AC0 GND (Bank 0) AE30 AE28 AE26 VCC AE24 AE22 AE20 AE18 AE16 GND AE14 VCCO0 AE12 GND (Bank 0) AE10 AE8 AE6 AE4 AE2 AE0 GCLK0 VCCJ GCLK1 GND TDI TMS Alternate Outputs Macrocell 1 AC27 AC26 AC25 AC24 AC23 AC22 AC21 AC20 AC19 AC18 AC17 AC16 AC15 AC14 AC13 AC12 AC11 AC10 AC9 AC8 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Macrocell 2 AE27 AE26 AE25 AE24 AE23 AE22 AE21 AE20 AE19 AE18 AE17 AE16 AE15 AE14 AE13 AE12 AE11 AE10 AE9 AE8 AE7 AE6 AE5 AE4 AE3 AE2 AE1 AE0 Alternate Input AC23 AC21 AC19 AC17 AC15 AC13 AC11 AC9 AC7 AC5 AC3 AC1 AE31 AE29 AE27 AE25 AE23 AE21 AE19 AE17 AE15 AE13 AE11 AE9 AE7 AE5 AE3 AE1 484 fpBGA Ball Number K6 VCCO0 K3 K5 K2 L5 K1 L6 L1 M5 L2 N5 VCCO0 L3 M6 M2 P5 VCC P6 M3 N6 N2 P1 GND N3 VCCO0 M8 N8 P2 P8 N4 H1 J1 N7 672 fpBGA Ball Number J5 VCCO0 J4 K7 L7 J3 J2 K6 L6 K5 K4 K3 VCCO0 K2 K1 L2 L5 VCC L4 L3 M3 M7 N7 GND M5 VCCO0 M4 M6 N6 M2 M1 N1 N2 N5 GND (Bank 0) GND (Bank 0) GND (Bank 0) GND (Bank 0) GND (Bank 0) GND (Bank 0) See Power Supply and NC Connections Table P7 GND R1 R2 N3 GND P4 P5 76 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 51024MX Logic Signal Connections (Continued) sysIO Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LVDS Pair 0P 0N 1P 1N 2P 2N 3P 3N 4P 4N 5P 5N 6P 6N 7P 7N 8P 8N 9P 9N 10P 10N 11P 11N 12P 12N 13P 13N 14P 14N 15P Primary Macrocell/Function TCK TDO A30 A28 A26 A24 A22 A20 GND (Bank 1) A18 VCCO1 A16 GND A14 VCC A12 A10 A8 A6 A4 A2 A0 GND (Bank 1) C30 VCCO1 C28 C26 C24 C22 C20 C18 C16 C14 C12 GND (Bank 1) C10 VCCO1 C8 GND C6 VCC C4 C2 Alternate Outputs Macrocell 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 Macrocell 2 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 Alternate Input A31 A29 A27 A25 A23 A21 A19 A17 A15 A13 A11 A9 A7 A5 A3 A1 C31 C29 C27 C25 C23 C21 C19 C17 C15 C13 C11 C9 C7 C5 C3 484 fpBGA Ball Number T1 V1 -- -- -- -- -- -- -- VCCO1 -- GND -- VCC -- -- -- -- -- -- -- -- VCCO1 -- -- -- -- -- -- -- -- -- -- VCCO1 -- GND -- VCC -- -- 672 fpBGA Ball Number P3 P2 P1 R1 P6 R6 P7 R7 R4 VCCO1 R5 GND R3 VCC R2 T2 T3 T4 T5 U2 U3 U4 VCCO1 U5 T6 U6 T7 U7 U1 V1 V2 V3 V5 VCCO1 V4 GND W2 VCC W3 W4 GND (Bank 1) GND (Bank 1) GND (Bank 1) GND (Bank 1) GND (Bank 1) GND (Bank 1) 77 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 51024MX Logic Signal Connections (Continued) sysIO Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LVDS Pair 15N 16P 16N 17P 17N 18P 18N 19P 19N 20P 20N 21P 21N 22P 22N 23P 23N 24P 24N 25P 25N 26P 26N 27P 27N 28P 28N 29P 29N 30P 30N Primary Macrocell/Function C0 E30/DATA0 E28/DATA1 E26/DATA2 E24/DATA3 E22/DATA4 E20/DATA5 GND (Bank 1) E18/DATA6 VCCO1 E16/DATA7 GND E14/INITB E12/CSB E10/READ E8/CCLK E6 VCC E4 E2 E0 F30 F28 GND (Bank 1) F26 VCCO1 F24 F22 F20 F18 DONE F14 F12 GND (Bank 1) F10 VCCO1 F8 F6 F4 F2 F0 PROGRAMB G28 G12 G13 G14 G15 H14 E12 E13 E14 E15 Alternate Outputs Macrocell 1 A31 G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 H0 H2 H4 H6 H8 H10 H12 Macrocell 2 C31 E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 Alternate Input C1 E31 E29 E27 E25 E23 E21 E19 E17 E15 E13 E11 E9 E7 E5 E3 E1 F31 F29 F27 F25 F23 F21 F19 F15 F13 F11 F9 F7 F5 F3 F1 G29 484 fpBGA Ball Number -- W1 Y1 P3 R3 T2 U2 V2 VCCO1 W2 GND R4 T4 R6 R5 U3 VCC V3 Y2 W3 U5 T5 U4 VCCO1 V4 AA3 AB3 Y4 AA4 AB2 U6 V5 VCCO1 W6 AB4 AB5 T6 U7 W5 U8 672 fpBGA Ball Number W5 W1 Y1 V6 W6 Y2 Y3 Y4 VCCO1 Y5 GND V7 W7 AA1 AA2 AA3 VCC AA4 Y6 AA5 AB2 AB3 AB4 VCCO1 AB5 AB1 AC2 AC3 AC4 AC1 AD1 AD2 VCCO1 AD3 Y8 Y9 AA8 AA9 AB8 AB9 GND (Bank 1) GND (Bank 1) GND (Bank 1) GND (Bank 1) GND (Bank 1) GND (Bank 1) 78 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 51024MX Logic Signal Connections (Continued) sysIO Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 LVDS Pair 31P 31N 32P 32N 33P 33N 34P 34N 35P 35N 36P 36N 37P 37N 38P 38N 39P 39N 40P 40N 41P 41N 42P 42N 43P 43N 44P 44N 45P 45N Primary Macrocell/Function GND (Bank 1) G26 VCCO1 G24 GND G22 VCC G20 G18 G16 G14 G12 G10 G8 G6 G4 GND (Bank 1) CFG0 VCCO1 G0 H30 H28 H26 H24 H22 H20 H18 H16/VREF1 H14 H12 GND (Bank 1) H10 VCCO1 H8 H6 GND H4 VCC H2 H0 I0 VCC I2 Alternate Outputs Macrocell 1 H16 H18 H20 H22 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 J0 J1 Macrocell 2 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 L0 L1 Alternate Input G27 G25 G23 G21 G19 G17 G15 G13 G11 G9 G7 G5 G1 H31 H29 H27 H25 H23 H21 H19 H17 H15 H13 H11 H9 H7 H5 H3 H1 I1 I3 484 fpBGA Ball Number V6 VCCO1 V7 GND Y5 VCC AA5 Y6 Y7 AA6 AA7 W7 V8 W8 U9 U10 VCCO1 AB7 AA8 AB8 AB9 W9 Y9 AB10 AA10 W10 Y10 Y11 V9 VCCO1 V10 AA11 GND AB11 VCC U11 V11 AB12 VCC AA12 672 fpBGA Ball Number AB7 VCCO1 AC7 GND AB6 VCC AC6 AC8 AC9 AC5 AD4 AD5 AD6 AD7 AD8 AE3 VCCO1 AD9 AD10 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AF3 AF4 AF5 VCCO1 AF6 AF7 GND AF8 VCC AF9 AF10 AF17 VCC AF18 GND (Bank 1) GND (Bank 1) GND (Bank 1) GND (Bank 1) GND (Bank 1) GND (Bank 1) 79 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 51024MX Logic Signal Connections (Continued) sysIO Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 LVDS Pair 46P 46N 47P 47N 48P 48N 49P 49N 50P 50N 51P 51N 52P 52N 53P 53N 54P 54N 55P 55N 56P 56N 57P 57N 58P 58N 59P 59N 60P 60N 61P 61N 62P 62N Primary Macrocell/Function GND I4 I6 I8 VCCO2 I10 GND (Bank 2) I12 I14 I16 I18/VREF2 I20 I22 I24 I26 I28 I30 J0 VCCO2 J2 GND (Bank 2) J4 J6 J8 J10 J12 J14 J16 J18 J20 VCC J22 GND J24 VCCO2 J26 GND (Bank 2) J28 J30 K0 K2 K4 K6 L13 L14 L15 L16 L17 L18 L19 Alternate Outputs Macrocell 1 J2 J3 J4 J5 J6 J7 L0 L1 J8 J9 J10 J11 J12 J13 J14 J15 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 Macrocell 2 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 I0 I2 I4 I6 I8 I10 I12 I16 I20 I22 Alternate Input I5 I7 I9 I11 I13 I15 I17 I19 I21 I23 I25 I27 I29 I31 J1 J3 J5 J7 J9 J11 J13 J15 J17 J19 J21 J23 J25 J27 J29 J31 K1 K3 K5 K7 484 fpBGA Ball Number GND Y12 AA13 V12 VCCO2 U12 AB13 Y13 V13 W13 V14 W14 Y14 AB14 AB15 AA15 U13 VCCO2 U14 W15 W16 Y16 AA16 AB16 AA17 Y17 AA18 W17 VCC W18 GND V15 VCCO2 U15 Y18 V17 V16 U16 AB18 AB19 672 fpBGA Ball Number GND AF19 AF20 AF21 VCCO2 AF22 AF23 AF24 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AD17 VCCO2 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AC22 AC21 AC18 VCC AC19 GND AC20 VCCO2 AB21 AB18 AB19 AB20 AA20 AA19 Y19 GND (Bank 2) GND (Bank 2) GND (Bank 2) GND (Bank 2) GND (Bank 2) GND (Bank 2) 80 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 51024MX Logic Signal Connections (Continued) sysIO Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 LVDS Pair 63P 63N 64P 64N 65P 65N 66P 66N 67P 67N 68P 68N 69P 69N 70P 70N 71P 71N 72P 72N 73P 73N 74P 74N 75P 75N 76P 76N 77P 77N 78P 78N 79P Primary Macrocell/Function K8 VCCO2 K10 GND (Bank 2) K12 K14 K16 K18 K20 K22 K24 VCCO2 K26 GND (Bank 2) K28 K30 L0 L2 L4 VCC L6 L8 L10 L12 L14 GND L16 VCCO2 L18 GND (Bank 2) L20 L22 L24 L26 L28 L30 N0 N2 N4 VCC N6 GND N8 Alternate Outputs Macrocell 1 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 J16 J17 J18 J19 L30 L31 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 P0 P1 P2 P3 P4 Macrocell 2 L16 L17 L18 L19 I24 I26 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 L30 L31 N0 N1 N2 N3 N4 Alternate Input K9 K11 K13 K15 K17 K19 K21 K23 K25 K27 K29 K31 L1 L3 L5 L7 L9 L11 L13 L15 L17 L19 L21 L23 L25 L27 L29 L31 N1 N3 N5 N7 N9 484 fpBGA Ball Number AA19 VCCO2 U17 V18 AB21 U18 T17 AB20 AA20 Y19 VCCO2 V19 T18 R17 U19 T19 V20 VCC U20 W20 Y21 R18 R19 GND W21 VCCO2 Y22 R20 P20 T21 R21 U21 V21 -- -- -- VCC -- GND -- 672 fpBGA Ball Number AA18 VCCO2 Y18 AD25 AD26 AC23 AC24 AC25 AC26 AB22 VCCO2 AB23 AB24 AB25 AB26 AA26 AA22 VCC Y21 AA23 AA24 AA25 Y26 GND Y22 VCCO2 Y23 W20 V20 W21 V21 Y24 Y25 W22 W23 W24 VCC W25 GND W26 GND (Bank 2) GND (Bank 2) GND (Bank 2) GND (Bank 2) GND (Bank 2) GND (Bank 2) 81 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 51024MX Logic Signal Connections (Continued) sysIO Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 LVDS Pair 79N 80P 80N 81P 81N 82P 82N 83P 83N 84P 84N 85P 85N 86P 86N 87P 87N 88P 88N 89P 89N 90P 90N 91P 91N 92P 92N GCLK3N Primary Macrocell/Function VCCO2 N10 GND (Bank 2) N12 N14 N16 N18 N20 N22 N24 N26 N28 VCCO2 N30 GND (Bank 2) P0 P2 P4 P6 P8 P10 P12 VCC P14 GND P16 VCCO2 P18 GND (Bank 2) P20 P22 P24 P26 P28 P30 TOE RESETB GOE0 GOE1 GNDP GCLK2 VCCP Alternate Outputs Macrocell 1 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 Macrocell 2 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 N26 N27 N28 N29 N30 N31 Alternate Input N11 N13 N15 N17 N19 N21 N23 N25 N27 N29 N31 P1 P3 P5 P7 P9 P11 P13 P15 P17 P19 P21 P23 P25 P27 P29 P31 484 fpBGA Ball Number VCCO2 -- -- -- -- -- -- -- -- -- -- VCCO2 -- -- -- -- -- -- -- -- VCC -- GND -- VCCO2 -- -- -- -- -- -- -- W22 V22 T22 R22 672 fpBGA Ball Number VCCO2 V26 V22 V23 V24 V25 U20 T20 U26 U25 U21 VCCO2 T21 U22 U23 U24 T24 T23 T22 T25 VCC R26 GND R25 VCCO2 R24 R21 P21 R22 R23 R20 P20 P25 P24 P23 P22 GND (Bank 2) GND (Bank 2) GND (Bank 2) GND (Bank 2) GND (Bank 2) GND (Bank 2) See Power Supply and NC Connections Table P16 N26 See Power Supply and NC Connections Table 82 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 51024MX Logic Signal Connections (Continued) sysIO Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 LVDS Pair GCLK3P 93N 93P 94N 94P 95N 95P 96N 96P 97N 97P 98N 98P 99N 99P 100N 100P 101N 101P 102N 102P 103N 103P 104N 104P 105N 105P 106N 106P 107N 107P 108N 108P 109N 109P Primary Macrocell/Function GCLK3 R0 R2 R4 R6 R8 R10 GND (Bank 3) R12 VCCO3 R14 GND R16 R18 R20 R22 R24 VCC R26 R28 R30 GND (Bank 3) T0 VCCO3 T2 T4 T6 T8 T10 T12 T14 T16 T18 GND (Bank 3) T20 VCCO3 T22 T24 T26 T28 T30/PLL_FBK1 U0/PLL_RST1 U2 Alternate Outputs Macrocell 1 T31 T30 T29 T28 T27 T26 T25 T24 T23 T22 T21 T20 T19 T18 T17 T16 T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0 X27 X26 Macrocell 2 R31 R30 R29 R28 R27 R26 R25 R24 R23 R22 R21 R20 R19 R18 R17 R16 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 V27 V26 Alternate Input R1 R3 R5 R7 R9 R11 R13 R15 R17 R19 R21 R23 R25 R27 R29 R31 T1 T3 T5 T7 T9 T11 T13 T15 T17 T19 T21 T23 T25 T27 T29 T31 U1 U3 484 fpBGA Ball Number N16 J22 H22 N19 P15 P21 N15 M15 VCCO3 N20 GND P22 N21 N17 M20 P17 VCC P18 M21 M17 L20 VCCO3 N18 L21 M18 L22 L17 K22 L18 K21 K18 K20 VCCO3 K17 K19 J17 E22 E21 G22 F21 672 fpBGA Ball Number N24 N23 N22 M26 M25 M23 M22 N20 VCCO3 M20 GND N21 M21 M24 L24 L23 VCC L22 L25 K26 K25 VCCO3 K24 K23 K22 J25 J24 L21 K21 L20 K20 J23 VCCO3 J22 J26 H26 H25 H24 H23 H22 GND (Bank 3) GND (Bank 3) GND (Bank 3) GND (Bank 3) GND (Bank 3) GND (Bank 3) 83 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 51024MX Logic Signal Connections (Continued) sysIO Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 LVDS Pair 110N 110P 111N 111P 112N 112P 113N 113P 114N 114P 115N 115P 116N 116P 117N 117P 118N 118P 119N 119P 120N 120P 121N 121P 122N 122P 123N 123P 124N 124P 125N 125P Primary Macrocell/Function GND (Bank 3) U4 VCCO3 U6 GND U8 U10 U12 U14/CLK_OUT1 U16 VCC U18 U20 U22 GND (Bank 3) U24 VCCO3 U26 U28 U30 GND V0 VCC V2 V4 V6 V8 V10 GND (Bank 3) V12 VCCO3 V14 V16 V18 V20 V22 V24 V26 V28 V30 W0 W2 GND (Bank 3) Alternate Outputs Macrocell 1 X25 X24 X23 X22 X21 X20 V31 V30 V29 V28 V27 V26 V25 V24 V23 V22 V21 V20 V19 V18 V17 V16 V15 V14 V13 V12 X19 X18 X17 X16 X31 X30 Macrocell 2 V25 V24 V23 V22 V21 V20 U30 U28 U26 V19 V18 V17 V16 V31 V30 Alternate Input U5 U7 U9 U11 U13 U15 U17 U19 U21 U23 U25 U27 U29 U31 V1 V3 V5 V7 V9 V11 V13 V15 V17 V19 V21 V23 V25 V27 V29 V31 W1 W3 484 fpBGA Ball Number H21 VCCO3 G21 GND D22 D21 J20 J19 E20 VCC F20 H17 H18 J18 VCCO3 H19 G20 G19 GND C22 VCC C21 D20 C19 F19 E19 G18 VCCO3 F18 B20 B19 A20 A19 D18 C18 G17 F16 E17 D17 672 fpBGA Ball Number J21 VCCO3 H21 GND G25 G24 G23 G22 J20 VCC H20 G26 F25 F24 VCCO3 F23 G21 F22 GND F26 VCC E26 E25 E24 E23 E22 D26 VCCO3 D25 D24 D23 C26 C25 G19 F19 G18 F18 F20 E20 GND (Bank 3) GND (Bank 3) GND (Bank 3) GND (Bank 3) GND (Bank 3) GND (Bank 3) GND (Bank 3) GND (Bank 3) 84 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 51024MX Logic Signal Connections (Continued) sysIO Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 0 0 LVDS Pair 126N 126P 127N 127P 128N 128P 129N 129P 130N 130P 131N 131P 132N 132P 133N 133P 134N 134P 135N 135P 136N 136P 137N 137P 138N 138P 139N 139P 140N 140P 141N 141P Primary Macrocell/Function W4 VCCO3 W6 GND W8 VCC W10 W12 W14 W16 W18 W20 W22 W24 W26 GND (Bank 3) W28 VCCO3 W30 X0 X2 X4 X6 X8 X10 X12/VREF3 X14 X16 X18 GND (Bank 3) X20 VCCO3 X22 X24 GND X26 VCC X28 X30 Y30 VCC Y28 GND Alternate Outputs Macrocell 1 V11 V10 V9 V8 V7 V6 V5 V4 V3 V2 V1 V0 X15 X14 X13 X12 X11 X10 X9 X8 X29 X28 X7 X6 X5 X4 X3 X2 X1 X0 Y31 Y30 Macrocell 2 U21 U20 U18 U16 U12 U10 U8 U6 U5 U4 U2 U0 V15 V14 V13 V12 V11 V10 V9 V8 V29 V28 V7 V6 V5 V4 V3 V2 V1 V0 AA31 AA30 Alternate Input W5 W7 W9 W11 W13 W15 W17 W19 W21 W23 W25 W27 W29 W31 X1 X3 X5 X7 X9 X11 X13 X15 X17 X19 X21 X23 X25 X27 X29 X31 Y31 Y29 484 fpBGA Ball Number B18 VCCO3 A18 GND C17 VCC B17 C16 B16 F13 F15 D16 E16 A16 A15 B15 VCCO3 A14 D15 E15 D14 F14 A13 B13 C14 E14 E13 F12 D13 VCCO3 C13 E12 GND C12 VCC B12 A12 E11 VCC C11 GND 672 fpBGA Ball Number E19 VCCO3 E18 GND C24 VCC C23 D22 D21 E21 D20 D19 D18 C22 C21 C20 VCCO3 C19 C18 C17 B24 B23 B22 B21 B20 B19 B18 B17 A24 VCCO3 A23 A22 GND A21 VCC A20 A19 A18 VCC A17 GND GND (Bank 3) GND (Bank 3) GND (Bank 3) GND (Bank 3) 85 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 51024MX Logic Signal Connections (Continued) sysIO Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVDS Pair 142N 142P 143N 143P 144N 144P 145N 145P 146N 146P 147N 147P 148N 148P 149N 149P 150N 150P 151N 151P 152N 152P 153N 153P 154N 154P 155N 155P 156N 156P 157N 157P 158N 158P Primary Macrocell/Function Y26 Y24 Y22 VCCO0 Y20 GND (Bank 0) Y18 Y16 Y14/VREF0 Y12 Y10 Y8 Y6 Y4 Y2 Y0 Z30 VCCO0 Z28 GND (Bank 0) Z26 Z24 Z22 Z20 Z18 Z16 Z14 Z12 Z10 VCC Z8 GND Z6 VCCO0 Z4 GND (Bank 0) Z2 Z0 AA30 AA28 AA26 AA24 Alternate Outputs Macrocell 1 Y29 Y28 Y27 Y26 Y25 Y24 Y3 Y2 Y23 Y22 Y21 Y20 Y19 Y18 Y1 Y0 AA29 AA28 AA27 AA26 AA25 AA24 AA23 AA22 AA21 AA20 AA19 AA18 AA17 AA16 AA15 AA14 AA13 AA12 Macrocell 2 AA29 AA28 AA27 AA26 AA25 AA24 AA3 AA2 AA23 AA22 AA21 AA20 AA19 AA18 AA1 AA0 Alternate Input Y27 Y25 Y23 Y21 Y19 Y17 Y15 Y13 Y11 Y9 Y7 Y5 Y3 Y1 Z31 Z29 Z27 Z25 Z23 Z21 Z19 Z17 Z15 Z13 Z11 Z9 Z7 Z5 Z3 Z1 AA31 AA29 AA27 AA25 484 fpBGA Ball Number B11 A11 F11 VCCO0 F10 E10 C10 D10 B10 A10 A9 C9 D9 F9 E9 A8 VCCO0 B8 A7 B7 A5 B5 B6 C7 E8 E7 E6 VCC D6 GND D8 VCCO0 F8 F7 D7 C6 C5 C4 D5 672 fpBGA Ball Number A10 A9 A8 VCCO0 A7 A6 A5 A4 A3 B10 B9 B8 B7 B6 B5 B4 VCCO0 B3 C10 C9 C8 C7 C6 C5 C4 D5 D9 VCC D8 GND D7 VCCO0 D6 F9 E9 F7 F8 G8 G9 GND (Bank 0) GND (Bank 0) GND (Bank 0) GND (Bank 0) GND (Bank 0) GND (Bank 0) 86 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet Global Clock LVDS pair options: GCLK0 and GCLK1, as well as GCLK2 and GCLK3, can be paired together to receive differential clocks; where GCLK0 and GCLK3 are the positive LVDS inputs. 87 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet Part Number Description LC XXXXX X X - XX XX XXX X Device Family LC Device Number 5256 = 256 Macrocells 5512 = 512 Macrocells 5768 = 768 Macrocells 51024 = 1,024 Macrocells Memory M Supply Voltage V = 3.3V B = 2.5V C = 1.8V Speed 4 = 4.0ns 45 = 4.5ns 5 = 5.0ns 52 = 5.2ns 75 = 7.5ns Grade C = Commercial I = Industrial Pin/Ball Count 208 256 484 672 Package F = fpBGA FN = Lead-Free fpBGA Q = PQFP Ordering Information Note: For voltage families offered in industrial temperature grades and for all but the slowest commercial speed grade, the speed grades on these devices are dual marked. For example, the commercial speed grade -45XXXXC is also marked with the industrial grade -75I. The commercial grade is always one speed grade faster than the associated dual mark industrial grade. The slowest commercial speed grade is marked as commercial grade only. Conventional Packaging ispXPLD 5000MC (1.8V) Commercial Devices Device LC5256MC Part Number LC5256MC-4F256C LC5256MC-5F256C LC5256MC-75F256C LC5512MC-45Q208C LC5512MC-75Q208C LC5512MC LC5512MC-45F256C LC5512MC-75F256C LC5512MC-45F484C LC5512MC-75F484C LC5768MC-5F256C LC5768MC LC5768MC-75F256C LC5768MC-5F484C LC5768MC-75F484C Macrocells Voltage (V) 256 256 256 512 512 512 512 512 512 768 768 768 768 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 tPD (ns) 4.0 5.0 7.5 4.5 7.5 4.5 7.5 4.5 7.5 5.0 7.5 5.0 7.5 Package fpBGA fpBGA fpBGA PQFP PQFP fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pin/Ball Count 256 256 256 208 208 256 256 484 484 256 256 484 484 I/O 141 141 141 149 149 193 193 253 253 193 193 317 317 Grade C C C C C C C C C C C C C 88 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5000MC (1.8V) Commercial Devices (Continued) Device Part Number LC51024MC-52F484C LC51024MC LC51024MC-75F484C LC51024MC-52F672C LC51024MC-75F672C Macrocells Voltage (V) 1024 1024 1024 1024 1.8 1.8 1.8 1.8 tPD (ns) 5.2 7.5 5.2 7.5 Package fpBGA fpBGA fpBGA fpBGA Pin/Ball Count 484 484 672 672 I/O 317 317 381 381 Grade C C C C ispXPLD 5000MC (1.8V) Industrial Devices Device LC5256MC Part Number LC5256MC-5F256I LC5256MC-75F256I LC5512MC-75Q208I LC5512MC LC5512MC-75F256I LC5512MC-75F484I LC5768MC LC51024MC LC5768MC-75F256I LC5768MC-75F484I LC51024MC-75F484I LC51024MC-75F672I Macrocells Voltage (V) 256 256 512 512 512 768 768 1024 1024 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 tPD (ns) 5.0 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 Package fpBGA fpBGA PQFP fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pin/Ball Count 256 256 208 256 484 256 484 484 672 I/O 141 141 149 193 253 193 317 317 381 Grade I I I I I I I I I ispXPLD 5000MB (2.5V) Commercial Devices Device LC5256MB Part Number LC5256MB-4F256C LC5256MB-5F256C LC5256MB-75F256C LC5512MB-45Q208C LC5512MB-75Q208C LC5512MB LC5512MB-45F256C LC5512MB-75F256C LC5512MB-45F484C LC5512MB-75F484C LC5768MB-5F256C LC5768MB LC5768MB-75F256C LC5768MB-5F484C LC5768MB-75F484C LC51024MB-52F484C LC51024MB LC51024MB-75F484C LC51024MB-52F672C LC51024MB-75F672C Macrocells Voltage (V) 256 256 256 512 512 512 512 512 512 768 768 768 768 1024 1024 1024 1024 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 tPD (ns) 4.0 5.0 7.5 4.5 7.5 4.5 7.5 4.5 7.5 5.0 7.5 5.0 7.5 5.2 7.5 5.2 7.5 Package fpBGA fpBGA fpBGA PQFP PQFP fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pin/Ball Count 256 256 256 208 208 256 256 484 484 256 256 484 484 484 484 672 672 I/O 141 141 141 149 149 193 193 253 253 193 193 317 317 317 317 381 381 Grade C C C C C C C C C C C C C C C C C ispXPLD 5000MB (2.5V) Industrial Devices Device LC5256MB Part Number LC5256MB-5F256I LC5256MB-75F256I Macrocells Voltage (V) 256 256 2.5 2.5 tPD (ns) 5.0 7.5 Package fpBGA fpBGA Pin/Ball Count 256 256 I/O 141 141 Grade I I 89 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5000MB (2.5V) Industrial Devices (Continued) Device LC5512MB Part Number LC5512MB-75Q208I LC5512MB-75F256I LC5512MB-75F484I LC5768MB LC51024MB LC5768MB-75F256I LC5768MB-75F484I LC51024MB-75F484I LC51024MB-75F672I Macrocells Voltage (V) 512 512 512 768 768 1024 1024 2.5 2.5 2.5 2.5 2.5 2.5 2.5 tPD (ns) 7.5 7.5 7.5 7.5 7.5 7.5 7.5 Package PQFP fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pin/Ball Count 208 256 484 256 484 484 672 I/O 149 193 253 193 317 317 381 Grade I I I I I I I ispXPLD 5000MV (3.3V) Commercial Devices Device LC5256MV Part Number LC5256MV-4F256C LC5256MV-5F256C LC5256MV-75F256C LC5512MV-45Q208C LC5512MV-75Q208C LC5512MV LC5512MV-45F256C LC5512MV-75F256C LC5512MV-45F484C LC5512MV-75F484C LC5768MV-5F256C LC5768MV LC5768MV-75F256C LC5768MV-5F484C LC5768MV-75F484C LC51024MV-52F484C LC51024MV LC51024MV-75F484C LC51024MV-52F672C LC51024MV-75F672C Macrocells Voltage (V) 256 256 256 512 512 512 512 512 512 768 768 768 768 1024 1024 1024 1024 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 tPD (ns) 4.0 5.0 7.5 4.5 7.5 4.5 7.5 4.5 7.5 5.0 7.5 5.0 7.5 5.2 7.5 5.2 7.5 Package fpBGA fpBGA fpBGA PQFP PQFP fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pin/Ball Count 256 256 256 208 208 256 256 484 484 256 256 484 484 484 484 672 672 I/O 141 141 141 149 149 193 193 253 253 193 193 317 317 317 317 381 381 Grade C C C C C C C C C C C C C C C C C ispXPLD 5000MV (3.3V) Industrial Devices Device LC5256MV Part Number LC5256MV-5F256I LC5256MV-75F256I LC5512MV-75Q208I LC5512MV LC5512MV-75F256I LC5512MV-75F484I LC5768MV LC51024MV LC5768MV-75F256I LC5768MV-75F484I LC51024MV-75F484I LC51024MV-75F672I Macrocells Voltage (V) 256 256 512 512 512 768 768 1024 1024 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 tPD (ns) 5.0 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 Package fpBGA fpBGA PQFP fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pin/Ball Count 256 256 208 256 484 256 484 484 672 I/O 141 141 149 193 253 193 317 317 381 Grade I I I I I I I I I 90 Lattice Semiconductor Lead-Free Packaging ispXPLD 5000MX Family Data Sheet ispXPLD 5000MC (1.8V) Lead-Free Commercial Devices Device LC5256MC Part Number LC5256MC-4FN256C LC5256MC-5FN256C LC5256MC-75FN256C LC5512MC-45FN256C LC5512MC LC5512MC-75FN256C LC5512MC-45FN484C LC5512MC-75FN484C LC5768MC-5FN256C LC5768MC LC5768MC-75FN256C LC5768MC-5FN484C LC5768MC-75FN484C LC51024MC-52FN484C LC51024MC LC51024MC-75FN484C LC51024MC-52FN672C LC51024MC-75FN672C Macrocells 256 256 256 512 512 512 512 768 768 768 768 1024 1024 1024 1024 Voltage (V) tPD (ns) 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 4.0 5.0 7.5 4.5 7.5 4.5 7.5 5.0 7.5 5.0 7.5 5.2 7.5 5.2 7.5 Package Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Pin/Ball Count 256 256 256 256 256 484 484 256 256 484 484 484 484 672 672 I/O 141 141 141 193 193 253 253 193 193 317 317 317 317 381 381 Grade C C C C C C C C C C C C C C C ispXPLD 5000MC (1.8V) Lead-Free Industrial Devices Device LC5256MC LC5512MC LC5768MC LC51024MC Part Number LC5256MC-5FN256I LC5256MC-75FN256I LC5512MC-75FN256I LC5512MC-75FN484I LC5768MC-75FN256I LC5768MC-75FN484I LC51024MC-75FN484I LC51024MC-75FN672I Macrocells 256 256 512 512 768 768 1024 1024 Voltage (V) tPD (ns) 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 5.0 7.5 7.5 7.5 7.5 7.5 7.5 7.5 Package Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Pin/Ball Count 256 256 256 484 256 484 484 672 I/O 141 141 193 253 193 317 317 381 Grade I I I I I I I I ispXPLD 5000MV (3.3V) Lead-Free Commercial Devices Device LC5256MV Part Number LC5256MV-4FN256C LC5256MV-5FN256C LC5256MV-75FN256C LC5512MV-45FN256C LC5512MV LC5512MV-75FN256C LC5512MV-45FN484C LC5512MV-75FN484C LC5768MV-5FN256C LC5768MV LC5768MV-75FN256C LC5768MV-5FN484C LC5768MV-75FN484C Macrocells 256 256 256 512 512 512 512 768 768 768 768 Voltage (V) tPD (ns) 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 4.0 5.0 7.5 4.5 7.5 4.5 7.5 5.0 7.5 5.0 7.5 Package Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Pin/Ball Count 256 256 256 256 256 484 484 256 256 484 484 I/O 141 141 141 193 193 253 253 193 193 317 317 Grade C C C C C C C C C C C 91 Lattice Semiconductor ispXPLD 5000MX Family Data Sheet ispXPLD 5000MV (3.3V) Lead-Free Commercial Devices (Continued) Device Part Number LC51024MV-52FN484C LC51024MV LC51024MV-75FN484C LC51024MV-52FN672C LC51024MV-75FN672C Macrocells 1024 1024 1024 1024 Voltage (V) tPD (ns) 3.3 3.3 3.3 3.3 5.2 7.5 5.2 7.5 Package Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Pin/Ball Count 484 484 672 672 I/O 317 317 381 381 Grade C C C C ispXPLD 5000MV (3.3V) Lead-Free Industrial Devices Device LC5256MV LC5512MV LC5768MV LC51024MV Part Number LC5256MV-5FN256I LC5256MV-75FN256I LC5512MV-75FN256I LC5512MV-75FN484I LC5768MV-75FN256I LC5768MV-75FN484I LC51024MV-75FN484I LC51024MV-75FN672I Macrocells 256 256 512 512 768 768 1024 1024 Voltage (V) tPD (ns) 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 5.0 7.5 7.5 7.5 7.5 7.5 7.5 7.5 Package Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Lead-free fpBGA Pin/Ball Count 256 256 256 484 256 484 484 672 I/O 141 141 193 253 193 317 317 381 Grade I I I I I I I I For Further Information In addition to this data sheet, the following technical notes may be helpful when designing with the ispXPLD 5000MX family: * sysIO Usage Guidelines for Lattice Devices (TN1000) * Lattice sysCLOCK PLL Design and Usage Guidelines (TN1003) * Power Estimation in ispXPLD 5000MX Devices (TN1031) * Using Memory in ispXPLD 5000MX Devices (TN1030) * ispXP Configuration Usage Guidelines (TN1026) 92 |
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